Design & Reuse
Catalog of SIP Cores
System on Chip design resources
8765 IP
551
30.0
zstd compression and decompression IP core
The zstd (Zstandard) compression algorithm is an advanced, lossless data compression technology. It has quickly become a popular choice for a variety ...
552
30.0
Quad core IP platform with integrated Arm security subsystem
Aion Silicon (formerly Sondrel) has created a powerful, quad core IP platform, the SFA 200, that is ideal for ASIC solutions for remote gathering and ...
553
30.0
NVM Express Host IP Core
The IPM-NVMe_Host core is a verilog IP to be integrated in a FPGA or ASIC design. It fully manages the NVMe and PCIe protocol on the host side without...
554
30.0
LZ4 compression and decompression IP core
The LZ4 compression algorithm is a fast, lossless data compression technology renowned for its high-speed performance and low latency. LZ4 offers impr...
555
29.1
Zinia Pixel Processor IP - PP300 Series
Allegro DVT’s PP300 IP is a flexible Pixel Processor that provides a wide range of processing functions. The PP300 IP offers various system integra...
556
29.1
Prism Video Encoder IP – E100 Series
Allegro DVT’s E100 Series of Encoder IP enables HD/1080P60 resolution encoding up to 5MPixels in a single core. The E100 Series Encoder is built ar...
557
29.1
Prism Video Encoder IP – E300 Series
Allegro DVT’s E300 Series of Encoder IP features a new hardware architecture that minimizes the silicon area while enabling 4K resolution encoding in ...
558
29.1
Prism Video Encoder IP – E301
E301 is the Allegro DVT’s MPEG-5 Low Complexity Enhancement Video Coding (LCEVC) encoder IP solution. The E301 LCEVC encoder IP is optimized for power...
559
29.1
Pulsar Video Decoder IP - D100 Series
D100 Series is the Allegro DVT’s ultimate multi-format, multi-stream real-time hardware decoder IP core, for all semiconductor manufacturers looking t...
560
29.1
Juno Neural Video Processor IP - NVP300 Series
Allegro DVT’s NVP300, AI-based Neural Video Processing IP push video quality to the next level by leveraging the advanced features and benefits of AI ...
561
29.0
USB V3.1 Power Delivery Type-C Port Evaluation board for OTI9108 IP
The OTS9106 board is a complete FPGA and ARM processor based USB PD Type-C port, featuring the RTL and C source code of the Obsidian Technology OTI910...
562
26.0
HDMI 2.0b IP Core
The Bitec HDMI 2.0b IP Core enables HDMI interconnectivity without the need for external HDMI ASSP devices. Supporting pixel clocks to 600Mhz, the IP ...
563
26.0
HDMI 2.1 IP Core
The Bitec HDMI 2.1b IP Core enables HDMI interconnectivity in FPGA or ASIC devices. Supporting uncompressed video formats to 8K60 4:2:0 and beyond for...
564
26.0
VESA Display Stream Compression (DSC) IP Core
Display Stream Compression offers inter-operable, visually lossless real-time, video compression to satisfy the emerging high bandwidth and high resol...
565
26.0
DisplayPort 1.4a IP Core
DisplayPort heralds a new alternative in video connectivity. Designed to enable low cost direct drive monitors and backed by industry leaders (Intel, ...
566
25.0
TSMC 12nm 16Gbps SerDes IP supporting multiple serial protocols
A high-performance, low-power 16Gbps SerDes IP supporting multiple serial protocols. Integrated PMA and PCS layers with advanced equalization and diag...
567
25.0
DVB-S2 Demodulator IP Core
DVBS2_DEMOD.vhd performs the demodulation based on three tracking loops: carrier tracking (for coherent demodulation), symbol timing tracking, and A...
568
23.3333
PCIe Gen6 Controller
The SignatureIP PCIe Controller IP is a silicon-proven, highly configurable controller designed for high-bandwidth, low-latency connectivity in next-g...
569
23.3333
Cloud-active NOC configuration tool for generating and simulating Coherent and Non-Coherent NoCs
iNoCulator is a cloud-active EDA tool that is used to define the topology of a NoC quickly and easily, configure its parameters and simulate it to mea...
570
23.3333
Coherent Network-on-chip (NoC) IP
C-NoC is a layered, scalable, configurable, and physically aware configurable NoC. It supports mesh, grid and torus topologies with simultaneous exist...
571
23.3333
Non-coherent Network-on-chip (NoC) IP
NC-NoC is a layered, scalable, physically aware configurable NoC supporting multiple clocking schemes for SoCs that do not require coherency. NC-NoC s...
572
21.0
Zero Additional Mask MTP IP, 2.2-5V 4kbit HHGrace 180BCD
LEE Flash ZT (ZT) achieves automotive grade temperature and quality grade. Perfect fit for trimming and parameter storage in Sensor, Power and Analo...
573
21.0
Embedded flash IP, 1.32V/3V PSMC 90nm
LEE Flash G1 (G1) is based on simple SONOS architecture and capable to scale down to 40nm and supports auto grade temperature and quality. G1 is cos...
574
21.0
Embedded flash IP, 1.5V/5V 130BCD Plus
LEE Flash G1 (G1) is based on simple SONOS architecture and capable to scale down to 40nm . G1 is best fit embedded flash IP to BCD nodes and it can...
575
21.0
Embedded flash IP, 1.5V/5V 130nm
LEE Flash G1 (G1) is based on simple SONOS architecture and capable to scale down to 40nm and supports auto grade temperature and quality. G1 is cos...
576
20.0
MAXVY MIPI CSI2 Receiver IP
The MIPI CSI-2 (Camera Serial Interface) defines an interface between a peripheral device (camera) and host processor (application engine) for mobile...
577
20.0
MAXVY MIPI DSI-2 Transmitter Interface IP
MIPI DSI-2 (Display Serial Interface) defines an interface between a peripheral device (camera) and host processor (application engine) for mobile dev...
578
20.0
PCIe 5.0 PHY IP for Storage and High-Bandwidth Connection
M31 PCIe 5.0 PHY IP provides high-performance, multi-lane capability and low power architecture for high-bandwidth applications. The PCIe 5.0 IP suppo...
579
20.0
UCIe Verification IP
Truechip's UCIe Verification IP provides an effective & efficient way to verify the UCIe components of an IP or SoC. Truechip's VIP is fully compliant...
580
20.0
Secure-IC's Securyzr™ Memory & Bus Protection IP Core
The Memory & Bus Protection IP Core module enables on-the-fly encryption/decryption and authentication to the external memory. It supports AHB/AXI sl...
581
20.0
AES-XTS encryption/decryption IP
SphinX is designed to accommodate the speed, latency and throughput requirements of high performance computer systems main memory / DRAM. The IP imple...
582
20.0
GH310 - 2D GPU IP / 2D Sprite Engine
GH310 is a 2D GPU IP that packages the 2D image rendering features available in the GSHARK-TAKUMI family IPs. This IP accelerates 2D graphics on embed...
583
20.0
TicoXS FIP Decoder IP core with JPEG XS and intoPIX Flawless Imaging Profile (FIP) – The newest codec for AV over IP with 100% quality and zero latency !
TicoXS FIP is the smart path to AV over IP. With low logic & low memory, it delivers together the interoperable JPEG XS lightweight low latency compre...
584
20.0
TicoXS FIP Encoder IP core with JPEG XS and intoPIX Flawless Imaging Profile (FIP) – The newest codec for AV over IP with 100% quality and zero latency !
TicoXS FIP is the smart path to AV over IP. With low logic & low memory, it delivers together the interoperable JPEG XS lightweight low latency compre...
585
20.0
MIPI M-PHY v4.1/v3.1 IP in TSMC(5nm, 6nm, 7nm, 12nm,16nm, 22nm, 28nm, 40nm, and 55nm)
MIPI M-PHY is a serial interface technology with high bandwidth capabilities, which is particularly developed for mobile applications to obtain low pi...
586
20.0
Image warping IP (distortion correction IP)
Built on TAKUMI's GPU IP expertise, TAKUMI’s Image Warping IP lines up hardware acceleration IP products that support a variety of different image war...
587
20.0
Image warping IP (Distortion Correction IP)
Integrating advanced on-the-fly coordinate transformation and image processing powered by GPU technologies - High-performance image warping IP (distor...
588
20.0
Image warping IP core
The image warping IP core TW100 builds on TAKUMI's graphics accelerator IP core family as an additional solution to a variety of distortion correcting...
589
20.0
NoC Silicon IP for RISC-V based chips supporting the TileLink protocol
Truechip's NoC Silicon IP provides chip designers and architects with an efficient way to connect multiple TileLink based master and slave devices wit...
590
20.0
NoC Silicon IP for RISC-V based chips supporting the TileLink protocol
Truechip's NoC Silicon IP provides chip designers and architects with an efficient way to connect multiple TileLink based master and slave devices wit...
591
20.0
Original Lossless codec IP core - Full HD 30fps@126MHz (1Sample/clk)
KJN-S1 is able to get Higher performance lossless Compression by original algorithm. This product achieves a smaller circuit scale and higher compress...
592
20.0
USB4 Gen3X2 and DP1.4 X4 PHY IP with Type-C connector support
M31 USB4 Gen3x2 transceiver IP provides a complete range of USB4 Gen3x2 host and peripheral applications up to 40Gbps. It is compliant with the PIPE5....
593
20.0
Multi Protocol Switch IP Core for Safe and Secure Ethernet Network
"The CetraC Switch IP core is the ideal solution to interconnect any Ethernet, TSN and ARINC 664 Part 7 (AFDX) equipment for safety critical applicati...
594
20.0
Multi Protocol Switch IP Core for Safe and Secure Ethernet Network
"The CetraC Switch IP core is the ideal solution to interconnect any TSN, Ethernet and ARINC 664 Part 7 (AFDX) equipment for safety critical applicati...
595
20.0
GV380S - 2D GPU IP (Vector graphics accelerator)
GV380S is a Gen.4 2.5D / 2D (vector graphics) GPU IP. With further advanced Gen.4 architecture for ultra-minimized CPU load and increased pixel perfor...
596
20.0
GV380T - 2D GPU IP (Vector graphics accelerator)
GV380T is a Gen.4 2.5D / 2D (vector graphics) GPU IP. With further advanced Gen.4 architecture for ultra-minimized CPU load and increased pixel perfor...
597
20.0
DVB-S2 LDPC BCH Decoder and Encoder IP Core
The DVB-S2 LDPC-BCH block is a powerful FEC (Forward Error Correction) subsystem for Digital Video Broadcasting via Satellite....
598
20.0
DVB-S2X LDPC BCH Decoder and Encoder IP Core
The DVB-S2X LDPC Decoder is a powerful FEC core decoder for Digital Video Broadcasting via Satellite. It implements extensions to the DVB-S2 design fo...
599
18.0
Bluetooth® Bluetooth Low Energy 6.2 PHY IP
The icyTRX-LE-22 is a compact, ultra-low-power Bluetooth® Low Energy 6.2 PHY IP core developed in 22nm CMOS technology. It is engineered for seamless ...
600
17.5
802.11ax STA mode IP
This IP includes a recommendation-compliant 802.11ax PHY layer C floating-point code for the Station (STA) mode. The code is integrated into a simulat...