751 3.0

AHB2APB Bridge IP Truechip's AHB2APB Bridge IP provides chip designers and architects, an efficient way to connect Different Bus Protocol based IPs with reduced latency...

752 3.0

Single Lane and Quad Lane 10Gbps USB3.1 PHY IP in GF 28SLP process TERMINUS CIRCUITS USB 3.1 GEN2 PHY is high performance, low power, low latency Single & Quad-Lane PHY that supports USB protocol and its signalling ne...

753 3.0

Single Lane and Quad Lane 10Gbps USB3.1 PHY IP in TSMC 28HPC process TERMINUS CIRCUITS USB 3.1 GEN2 PHY is high performance, low power, low latency Single & Quad-Lane PHY that supports USB protocol and its signalling ne...

754 3.0

Single Lane and Quad Lane 10Gbps USB3.1 PHY IP in TSMC 55LP process TERMINUS CIRCUITS USB 3.1 GEN2 PHY is high performance, low power, low latency Single & Quad-Lane PHY that supports USB protocol and its signalling ne...

755 3.0

Single Lane and Quad Lane 10Gbps USB3.1 PHY IP in TSMC 65GP process TERMINUS CIRCUITS USB 3.1 GEN2 PHY is high performance, low power, low latency Single & Quad-Lane PHY that supports USB protocol and its signalling ne...

756 3.0

Single Lane and Quad Lane 16Gbps PCIe4.0 PHY IP in TSMC 28HPC process TERMINUS CIRCUITS PCIe GEN4.0 PHY is high performance, low power, low latency Single & Quad-Lane PCI Express PHY that supports PCI Express protocol an...

757 3.0

Single Lane and Quad Lane 5Gbps PCIe2.0 PHY IP in GF 28SLP process TERMINUS CIRCUITS PCIe GEN2.0 PHY is high performance, low power, low latency Single & Quad-Lane PCI Express PHY that supports PCI Express protocol a...

758 3.0

Single Lane and Quad Lane 5Gbps PCIe2.0 PHY IP in TSMC 28HPC process TERMINUS CIRCUITS PCIe GEN2.0 PHY is high performance, low power, low latency Single & Quad-Lane PCI Express PHY that supports PCI Express protocol an...

759 3.0

Single Lane and Quad Lane 5Gbps PCIe2.0 PHY IP in TSMC 55LP process TERMINUS CIRCUITS PCIe GEN2.0 PHY is high performance, low power, low latency Single & Quad-Lane PCI Express PHY that supports PCI Express protocol an...

760 3.0

Single Lane and Quad Lane 5Gbps PCIe2.0 PHY IP in TSMC 65GP process TERMINUS CIRCUITS PCIe GEN2.0 PHY is high performance, low power, low latency Single & Quad-Lane PCI Express PHY that supports PCI Express protocol an...

761 3.0

Single Lane and Quad Lane 5Gbps USB3.1 PHY IP in GF 28SLP process TERMINUS CIRCUITS USB 3.1 GEN1 PHY is high performance, low power, low latency Single & Quad-Lane PHY that supports USB protocol and its signalling ne...

762 3.0

Single Lane and Quad Lane 5Gbps USB3.1 PHY IP in TSMC 28HPC process TERMINUS CIRCUITS USB 3.1 GEN1 PHY is high performance, low power, low latency Single & Quad-Lane PHY that supports USB protocol and its signalling ne...

763 3.0

Single Lane and Quad Lane 5Gbps USB3.1 PHY IP in TSMC 55LP process TERMINUS CIRCUITS USB 3.1 GEN1 PHY is high performance, low power, low latency Single & Quad-Lane PHY that supports USB protocol and its signalling ne...

764 3.0

Single Lane and Quad Lane 5Gbps USB3.1 PHY IP in TSMC 65GP process TERMINUS CIRCUITS USB 3.1 GEN1 PHY is high performance, low power, low latency Single & Quad-Lane PHY that supports USB protocol and its signalling ne...

765 3.0

Single Lane and Quad Lane 8Gbps PCIe3.0 PHY IP in GF 28SLP process TERMINUS-CIRCUITS PCIe GEN3.0 PHY is high performance, low power, low latency Single &Quad-Lane PCI Express PHY that supports PCI Express protocol and...

766 3.0

Single Lane and Quad Lane 8Gbps PCIe3.0 PHY IP in TSMC 28HPC process TERMINUS CIRCUITS PCIe GEN3.0 PHY is high performance, low power, low latency Single & Quad-Lane PCI Express PHY that supports PCI Express protocol an...

767 3.0

Single Lane and Quad Lane 8Gbps PCIe3.0 PHY IP in TSMC 65G process TERMINUS CIRCUITS PCIe GEN3.0 PHY is high performance, low power, low latency Single & Quad-Lane PCI Express PHY that supports PCI Express protocol an...

768 3.0

MIPI RFFE Master IP SmartDV’s MIPI RFFE (Radio Frequency Front-End) Master IP is a silicon-proven solution designed for high-speed, low-latency control of RF front-end co...

769 3.0

MIPI SPMI Slave IP SmartDV’s MIPI SPMI (System Power Management Interface) Slave IP is a silicon-proven solution tailored for efficient communication with power manageme...

770 3.0

Complete measurement analog front end (AFE) IP for single phase power metering in TSMC 40uLPeF METRO-PM-MFE-mono.11-HD-IVT_TSMC_40_uLPeF is a Mixed-signal (analog and digital) Virtual Component in TSMC 40uLPeF. It is comprised of a high resoluti...

771 3.0

Complete measurement analog front end (AFE) IP for three-phase power metering in SMIC 40LL-RF METRO-PM-JADE-3P.11-HD_SMIC_40_LL-RF is a Mixed signal (analog and digital) Virtual Component in SMIC 40LL-RF which offers a complete analog front-end...

772 3.0

Complete measurement analog front end (AFE) IP for three-phase power metering in TSMC 40uLPeF METRO-PM-JADE-3P.11-HD_TSMC_40_uLPeF is a Mixed-signal (analog and digital) Virtual Component in TSMC 40uLPeF. It is comprised of a high resolution Mi...

773 3.0

complete measurement subsystem IP for single phase power meteringi in HHGrace 130eF Metro-Jade-PM-mono-10-HD-OV_HHGrace_130_eF is a Mixed signal (analog and digital) Virtual Component in HHGrace 130eF which offers a complete analog fr...

774 3.0

LPDDR2/3/4/4x IP combo solution with high performance and low power With sophisticated architecture and advanced technology, this LPDDR2/3/4/4x IP combo solution with high performance and low power. In 12~28nm CMOS pro...

775 3.0

USB 2.0 (LS, FS & HS) On-The-Go IP Core A 'Dual-Role' USB On-The-Go IP Core that operates as both an USB peripheral or as an USB OTG host in a point-to-point communications with another USB ...

776 2.5

FAT32 IP Soft Core for NVMe FAT32 IP Soft Core for NVMe...

777 2.5

SATA 3 HOST IP on ARRIA 10 FPGA The LDS-SATA3-HOST-A10GX IP incorporates the Transport layer, the Link layer, the PHY layer and the Rate Match FIFO on a INTEL ARRIA 10 GX FPGA. The L...

778 2.5

LDS SATA RECORDER IP ON ARTIX 7 ...

779 2.5

Xilinx Kintex 7 NVME HOST IP The LDS NVME HOST IP has been done for beginners and expert in NVMe to drive NVMe PCIe SSD....

780 2.5

Xilinx Ultra Scale NVME Host IP The LDS NVME HOST K7U IP is one of the most flexible NVME HOST IP in the market. It has been done for beginners and expert in NVMe to drive NVMe PC...

781 2.5

Xilinx Ultra Scale Plus SATA HOST IP The LDS_SATA3_HOST_GTHE4 IP incorporates the Transport layer, the Link layer and the PHY layer on a Xilinx Ultra Scale Plus GTHE4 FPGA. The LDS_SATA3_...

782 2.5

Xilinx ZYNQ NVME HOST IP The LDS NVME HOST IP has been done for beginners and expert in NVMe to drive NVMe PCIe SSD....

783 2.2581

2 separated LDO blocks IP ISTS_LDO2CH_S40V33 The ISTS_LDO2CH_S40V33 IP includes 2 separated LDO blocks to generate the power for PLL and 2.5V analog power application....

784 2.2581

Very low power IP with BOR/POR features embedded The IST-POR02 IP is a very low power IP with BOR/POR features embedded. It detects the voltage level of core power DVDD and IO power AVDD. When AVDD r...

785 2.2581

Very low power IP with VDT/POR features embedded The IST-POR05 IP is a very low power IP with VDT/POR features embedded. It detects the voltage level of IO power AVDD and core power. When AVDD rises ...

786 2.2581

Always on LDO IP IST-LDO33T15 The IST-LDO33T15 IP is a always on LDO to generate the power for Fuse, PLL, etc. application....

787 2.0

MAC Privacy Protection IP The MAC Privacy Protection IP is a fully compliant solution that provides Ethernet Layer 2 Security for port and data privacy as standardized in IEEE ...

788 2.0

MIPI A-PHY Verification IP MIPI A-PHY v1.0 is a physical layer communication protocol designed for automotive applications, including driver assistance, autonomous driving, and ...

789 2.0

Graphics Processor Overlay IP Core The GPU_OVERLAY IP Core (Figure 1) is a highly versatile on-screen display processor that allows high-quality anti-aliased bitmap graphics and text to...

790 1.0

3.6Kbit EEPROM IP with configuration 28p8w16bit GF130_EEPROM_01 is a nonvolatile electrically erasable programmable read-only memory (EEPROM) with volume 3.6Kbit, which is organized as 28 pages of 8...

791 1.0

1024-bit EEPROM IP with configuration 32p2w16bit The block is a nonvolatile electrically erasable programmable read-only memory (EEPROM) with volume 1024 bits (16(bit per word) x 2(word per page) x 3...

792 1.0

36Kbyte EEPROM IP with configuration 288p32w32bit The block is a nonvolatile electrically erasable programmable read-only memory (EEPROM) with volume 36Kbyte (32(bit per word) x 32(words per page) x 2...

793 1.0

36Kbyte EEPROM IP with configuration 288p32w32bit and oscillator 130GF_EEPROM_07 is a nonvolatile electrically erasable programmable read-only memory with volume 36Kbyte (32(bit per word) x 32(words per page) x 288(...

794 1.0

SATA HOST Synchronous IP The LDS SATA HOST XV5 IP incorporates the Transport layer, the Link layer and the PHY layer on a Xilinx Virtex 5 FPGA. The LDS SATA HOST XV5 IP is com...

795 1.0

2D Compostion Processing IP Vivancte 2D GPU processors provide high performance multi-surface composition which take all visual components of a screen, and processes and combines...

796 1.0

2D Compostion Processing IP Vivancte 2D GPU processors provide high performance multi-surface composition which take all visual components of a screen, and processes and combines...

797 1.0

2D Compostion Processing IP Vivancte 2D GPU processors provide high performance multi-surface composition which take all visual components of a screen, and processes and combines...

798 1.0

2D Compostion Processing IP Vivancte 2D GPU processors provide high performance multi-surface composition which take all visual components of a screen, and processes and combines...

799 1.0

HDMI1.4 Transmitter IP Innosilicon HDMI TX IP is designed for transmitting video and audio data from a video source device to a display device, which is compatible with HDMI...

800 1.0

VeriSilicon 400MHz 802.15.4g RF IP LIGHT is a RF IP supporting general modulation modes on 433MHz~510MHz band. The IP is designed to support 3.3V operation voltage with SMIC 55nm proces...