Logic Fruit Technologies IP Cores

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801

0.118

UMC 28nm HPM/LVT Logic Process 9-track Standard Generic Core cell library (C31)

UMC 28nm HPM/LVT Logic Process 9-track Standard Generic Core cell library (C31)...

802

0.118

UMC 28nm HPM/LVT Logic Process 9-track Standard Generic core cell library (C35)

UMC 28nm HPM/LVT Logic Process 9-track Standard Generic core cell library (C35)...

803

0.118

UMC 28nm HPM/RVT Logic and Mixed-Mode Process 12-track generic cell library

UMC 28nm HPM/RVT Logic and Mixed-Mode Process 12-track generic cell library...

804

0.118

UMC 28nm HPM/RVT Logic and Mixed-Mode Process 12-track generic cell library

UMC 28nm HPM/RVT Logic and Mixed-Mode Process 12-track generic cell library...

805

0.118

UMC 28nm HPM/RVT Logic and Mixed-Mode Process 12-track powerslash_core library

UMC 28nm HPM/RVT Logic and Mixed-Mode Process 12-track powerslash_core library...

806

0.118

UMC 28nm HPM/RVT Logic and Mixed-Mode Process 7-track eco_m1 cell library

UMC 28nm HPM/RVT Logic and Mixed-Mode Process 7-track eco_m1 cell library...

807

0.118

UMC 28nm HPM/RVT Logic and Mixed-Mode Process 7-track generic core cell library

UMC 28nm HPM/RVT Logic and Mixed-Mode Process 7-track generic core cell library...

808

0.118

UMC 28nm HPM/RVT Logic and Mixed-Mode Process 7-track Genernic Core cell library with LMINUS (C31 RVT)

UMC 28nm HPM/RVT Logic and Mixed-Mode Process 7-track Genernic Core cell library with LMINUS (C31 RVT)...

809

0.118

UMC 28nm HPM/RVT Logic and Mixed-Mode Process 7-track Genernic Core cell library with with LPLUS (C38 RVT)

UMC 28nm HPM/RVT Logic and Mixed-Mode Process 7-track Genernic Core cell library with with LPLUS (C38 RVT)...

810

0.118

UMC 28nm HPM/RVT Logic and Mixed-Mode Process 7-track Power Slash cell library

UMC 28nm HPM/RVT Logic and Mixed-Mode Process 7-track Power Slash cell library...

811

0.118

UMC 28nm HPM/RVT Logic Process 12-track generic cell library with LPLUS (C38)

UMC 28nm HPM/RVT Logic Process 12-track generic cell library with LPLUS (C38)...

812

0.118

UMC 28nm HPM/RVT Logic Process 12-track generic cell library with LPLUS (C38)

UMC 28nm HPM/RVT Logic Process 12-track generic cell library with LPLUS (C38)...

813

0.118

UMC 28nm HPM/RVT Logic Process 12-track generic_core library with LMINUS (C31)

UMC 28nm HPM/RVT Logic Process 12-track generic_core library with LMINUS (C31)...

814

0.118

UMC 28nm HPM/RVT Logic Process 9-track ECO_M1 core cell library (C31)

UMC 28nm HPM/RVT Logic Process 9-track ECO_M1 core cell library (C31)...

815

0.118

UMC 28nm HPM/RVT Logic Process 9-track Standard ECO_M1 CORE cell library (C38)

UMC 28nm HPM/RVT Logic Process 9-track Standard ECO_M1 CORE cell library (C38)...

816

0.118

UMC 28nm HPM/RVT Logic Process 9-track Standard Generic Core cell library (C31)

UMC 28nm HPM/RVT Logic Process 9-track Standard Generic Core cell library (C31)...

817

0.118

UMC 28nm HPM/RVT Logic Process 9-track Standard generic core cell library (C38)

UMC 28nm HPM/RVT Logic Process 9-track Standard generic core cell library (C38)...

818

0.118

UMC 28nm Logic and Mixed-Mode HLP/RVT Process, 1.05V Analog ESD IO cell Library

UMC 28nm Logic and Mixed-Mode HLP/RVT Process, 1.05V Analog ESD IO cell Library...

819

0.118

UMC 28nm Logic and Mixed-Mode HLP/RVT Process, 1.8V Analog ESD IO cell Library

UMC 28nm Logic and Mixed-Mode HLP/RVT Process, 1.8V Analog ESD IO cell Library...

820

0.118

UMC 28nm Logic and Mixed-Mode HPC Process 3.3V Analog ESD IO cell Library

UMC 28nm Logic and Mixed-Mode HPC Process 3.3V Analog ESD IO cell Library...

821

0.118

UMC 28nm Logic and Mixed-Mode HPC Process, 1.8V Analog ESD IO cell Library

UMC 28nm Logic and Mixed-Mode HPC Process, 1.8V Analog ESD IO cell Library...

822

0.118

UMC 28nm Logic and Mixed-Mode HPC Process,0.9V Analog ESD IO cell Library

UMC 28nm Logic and Mixed-Mode HPC Process,0.9V Analog ESD IO cell Library...

823

0.118

UMC 28nm Logic and Mixed-Mode HPC Processs Multi-Voltage BOAC SD3.0 I/O Cell library

UMC 28nm Logic and Mixed-Mode HPC Processs Multi-Voltage BOAC SD3.0 I/O Cell library...

824

0.118

UMC 28nm Logic and Mixed-Mode Low-K HPC Process 1.8V BOAC I/O Cell library

UMC 28nm Logic and Mixed-Mode Low-K HPC Process 1.8V BOAC I/O Cell library...

825

0.118

UMC 28nm Logic and Mixed-Mode Low-K HPC Process True 1.8V High Frequency Oscillator BOAC IO Cell Library

UMC 28nm Logic and Mixed-Mode Low-K HPC Process True 1.8V High Frequency Oscillator BOAC IO Cell Library...

826

0.118

UMC 28nm Logic and Mixed-Mode Low-K HPC Process True 1.8V Low Power Low Frequency OSC IO Cell Library

UMC 28nm Logic and Mixed-Mode Low-K HPC Process True 1.8V Low Power Low Frequency OSC IO Cell Library...

827

0.118

UMC 28nm Logic process standard synchronous LVT periphery high density single port SRAM memory compiler.

UMC 28nm Logic process standard synchronous LVT periphery high density single port SRAM memory compiler....

828

0.118

UMC 28nm Logic process standard synchronous LVT periphery high density single port SRAM memory compiler.

UMC 28nm Logic process standard synchronous LVT periphery high density single port SRAM memory compiler....

829

0.118

UMC 28nm Logic process standard synchronous RVT periphery high density single port SRAM memory compiler with row redundancy.

UMC 28nm Logic process standard synchronous RVT periphery high density single port SRAM memory compiler with row redundancy....

830

0.118

UMC 28nm Logic process standard synchronous RVT periphery high density single port SRAM memory compiler.

UMC 28nm Logic process standard synchronous RVT periphery high density single port SRAM memory compiler....

831

0.118

UMC 40nm Logic process standard Synchronous High Density Two Port Register File SRAM memory compiler.

UMC 40nm Logic process standard Synchronous High Density Two Port Register File SRAM memory compiler....

832

0.118

UMC 40nm LP Logic Process Dual-Port SRAM Memory Compiler with LVT peripheral

UMC 40nm LP Logic Process Dual-Port SRAM Memory Compiler with LVT peripheral...

833

0.118

UMC 40nm LP Logic Process Dual-Port SRAM memory compiler with redundancy

UMC 40nm LP Logic Process Dual-Port SRAM memory compiler with redundancy...

834

0.118

UMC 40nm LP Logic Process Dual-Port SRAM memory compiler with redundancy and LVT peripheral

UMC 40nm LP Logic Process Dual-Port SRAM memory compiler with redundancy and LVT peripheral...

835

0.118

UMC 40nm LP Logic Process one-port register file for area optimize with HVT peripheral

UMC 40nm LP Logic Process one-port register file for area optimize with HVT peripheral...

836

0.118

UMC 40nm LP Logic Process one-port register file for area optimize with LVT peripheral

UMC 40nm LP Logic Process one-port register file for area optimize with LVT peripheral...

837

0.118

UMC 40nm LP Logic Process Single Port SRAM memory compiler using 213 bit -cell with peri-HVT

UMC 40nm LP Logic Process Single Port SRAM memory compiler using 213 bit -cell with peri-HVT...

838

0.118

UMC 40nm LP Logic Process Single Port SRAM Memory Compiler using 213 bit-cell with Peri-LVT

UMC 40nm LP Logic Process Single Port SRAM Memory Compiler using 213 bit-cell with Peri-LVT...

839

0.118

UMC 40nm LP Logic Process standard synchronous high density dual port SRAM memory compiler with LVT

UMC 40nm LP Logic Process standard synchronous high density dual port SRAM memory compiler with LVT...

840

0.118

UMC 40nm LP Logic Process standard synchronous high density dual port SRAM memory compiler with ROW redundancy with LVt peripheral

UMC 40nm LP Logic Process standard synchronous high density dual port SRAM memory compiler with ROW redundancy with LVt peripheral...

841

0.118

UMC 40nm LP Logic Process TCAM with LVT peripheral memory compiler

UMC 40nm LP Logic Process TCAM with LVT peripheral memory compiler...

842

0.118

UMC 40nm LP Logic Process Two-Port Register File with LVT Peripheral Memory Compiler

UMC 40nm LP Logic Process Two-Port Register File with LVT Peripheral Memory Compiler...

843

0.118

UMC 40nm LP Logic Process ULL Single Port SRAM Memory Compiler using 213 bit-cell with peri-HVT

UMC 40nm LP Logic Process ULL Single Port SRAM Memory Compiler using 213 bit-cell with peri-HVT...

844

0.118

UMC 40nm LP Logic Process ULL Single Port SRAM Memory Compiler using 213 bit-cell with peri-LVT

UMC 40nm LP Logic Process ULL Single Port SRAM Memory Compiler using 213 bit-cell with peri-LVT...

845

0.118

UMC 40nm LP Logic Process Ultra High Speed One-Port Register File_x005F_x005F_x005F_x005F_x005F_x000D_

UMC 40nm LP Logic Process Ultra High Speed One-Port Register File...

846

0.118

UMC 40nm LP LowK Logic Process ULL Dual-Port SRAM Memory Compiler with Peri-LVT

UMC 40nm LP LowK Logic Process ULL Dual-Port SRAM Memory Compiler with Peri-LVT...

847

0.118

UMC 40nm LP/HVT Logic Process SYNS-like 9T ECO_M1 Cell Library

UMC 40nm LP/HVT Logic Process SYNS-like 9T ECO_M1 Cell Library...

848

0.118

UMC 40nm LP/HVT Logic Process SYNS-like 9T GENERIC CORE Cell Library

UMC 40nm LP/HVT Logic Process SYNS-like 9T GENERIC CORE Cell Library...

849

0.118

UMC 40nm LP/HVT Logic Process SYNS-like 9T POWERSLASH Cell Library

UMC 40nm LP/HVT Logic Process SYNS-like 9T POWERSLASH Cell Library...

850

0.118

UMC 40nm LP/LVT Logic Process SYNS-like 9T ECO_M1 Cell Library

UMC 40nm LP/LVT Logic Process SYNS-like 9T ECO_M1 Cell Library...

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