Design & Reuse
3869 IP
3501
0.118
LVDS Transmitter IP, 8MHz - 100MHz, 4 channels, UMC 0.18um G2 process
3.3V 4 channel LVDS Transmitter 8~100MHz, UMC 90nm SP/RVT Low-K process....
3502
0.118
LVDS Transmitter IP, 8MHz - 135MHz, 4 channels, UMC 0.13um SP/FSG process
2.5V 4 channel LVDS Transmitter 8~135MHz, UMC 90nm SP/RVT Low-K process....
3503
0.118
LVDS Transmitter IP, 1200Mbps, UMC 55nm SP process
1.8V Sub-LVDS Transmitter 1200Mbps, UMC 40nm LP/RVT Logic process....
3504
0.118
LVDS Transmitter IP, 16MHz - 178MHz, UMC 55nm SP process
2.5V LVDS Transmitter 16~178MHz, UMC 55nm SP/RVT Low-K Logic process....
3505
0.118
LVDS Transmitter IP, 700Mbps, UMC 0.13um SP/FSG process
3.3V LVDS Transmitter 700Mbps, UMC 90nm SP/RVT low-L process....
3506
0.118
LVDS Transmitter IP, 700Mbps, UMC 55nm SP process
2.5V LVDS Transmitter 700Mbps, UMC 40nm LP Low-K Logic process....
3507
0.118
LVDS Transmitter IP, 700Mbps, UMC 90nm SP process
2.5V LVDS Transmitter 700Mbps, UMC 55nm SP Low-K Logic process....
3508
0.118
LVDS Transmitter IP, 700Mbps, UMC 90nm SP process
3.3V LVDS Transmitter 700Mbps, UMC 55nm SP/RVT Low-K process....
3509
0.118
LVDS Transmitter IP, 85MHz, UMC 55nm SP process
1.8V/3.3V 85MHz 35:5 LVDS Transmitter, UMC 0.18um GII Logic process....
3510
0.118
LVDS Transmitter IP, 8MHz - 135MHz , UMC 0.13um HS/FSG process
8M~135MHz DLL-based LVDS TX, UMC 0.13um HS/FSG process....
3511
0.118
LVDS Transmitter IP, 8MHz - 135MHz, UMC 90nm SP process
2.5V LVDS Transmitter 8~135MHz, UMC 90nm SP process....
3512
0.118
LVDS Transmitter IP, Tx IO, UMC 55nm SP process
0.18um TX PAD, UMC 0.18um Logic RVT-FSG process....
3513
0.118
LVDS Tx IO IP, 1.25GHz, UMC 90nm SP process
Single Port LVDS Transmitter PAD 1.25Gbps, UMC 90nm SP/RVT Low-K process....
3514
0.118
LVDS Tx IO IP, UMC 0.35um Logic process
0.13um LVDS TX IO PAD, UMC 0.13um HS/HVT-FSG process....
3515
0.118
LVDS Tx IO IP, UMC 90nm SP process
LVDS TX Pad, UMC 0.35um Logic process....
3516
0.118
Two Port OTG USB2.0 PHY;BOAC version; Wire bonding;UMC 40 nm LP/RVT process.
Two Port OTG USB2.0 PHY;BOAC version; Wire bonding;UMC 40 nm LP/RVT process....
3517
0.118
Two Port Register File Compiler IP, UMC 0.11um eFlash/HS process
UMC 0.11um eFlash HS process, Two Port Register File....
3518
0.118
Two Port Register File Compiler IP, UMC 0.11um HS/AE process
UMC 0.11um HS/AE (AL Advanced Enhancement) Logic process synchronous Two Port Register File memory compiler....
3519
0.118
Two Port Register File Compiler IP, UMC 0.11um HS/FSG process
UMC 0.11um HS Logic process synchronous Two Port Register File SRAM memory compiler....
3520
0.118
Two Port Register File Compiler IP, UMC 0.11um HS/FSG process
UMC 0.11um HS/FSG Logic process Synchronous Two Port Register File with 339cell memory compiler....
3521
0.118
Two Port Register File Compiler IP, UMC 0.11um LL process
UMC 0.11um AE/LL eFlash process Two Port Register File....
3522
0.118
Two Port Register File Compiler IP, UMC 0.11um LL/AE process
UMC 0.11um LL/AE (AL Advanced Enhancement) Logic process synchronous high density Two Port Register File SRAM memory compiler....
3523
0.118
Two Port Register File Compiler IP, UMC 0.11um LL/FSG process
UMC 0.11um Logic(LL) FSG process synchronous Two Port Register File memory compiler....
3524
0.118
Two Port Register File Compiler IP, UMC 0.11um SP/AE process
UMC 0.11um SP/AE (AL Advance Enhancement) Logic process synchronous Two Port SRAM memory compiler....
3525
0.118
Two Port Register File Compiler IP, UMC 0.13um HS/FSG process
UMC 0.13um HS/LL fusion (FSG) process high density synchronous Two Port Register File SRAM memory compiler....
3526
0.118
Two Port Register File Compiler IP, UMC 0.13um HS/FSG process
UMC 0.13um HS/FSG Logic process Synchronous Two Port Register File SRAM memory compiler....
3527
0.118
Two Port Register File Compiler IP, UMC 0.13um HS/FSG process
UMC 0.13um Logic HS FSG Synchronous high density Low Power Two Port Register File SRAM memory compiler....
3528
0.118
Two Port Register File Compiler IP, UMC 0.13um LL process
UMC 0.13um LL Logic/FSG process high density synchronous Two Port Register File SRAM memory compiler....
3529
0.118
Two Port Register File Compiler IP, UMC 0.13um SP/FSG process
UMC 0.13um SP/FSG Logic process synchronous Two Port (1R1W) Register File SRAM memory compiler....
3530
0.118
Two Port Register File Compiler IP, UMC 0.153um MS process
UMC 0.153um Mixed-Mode/Logic process synchronous Two Port (1R1W) Register File SRAM memory compiler....
3531
0.118
Two Port Register File Compiler IP, UMC 0.162um Logic process
UMC 0.162um Logic process synchronous Two Port Register File SRAM memory compiler....
3532
0.118
Two Port Register File Compiler IP, UMC 0.18um G2 process
UMC 0.18um GII Logic process synchronous Two Port (1R1W) Register File SRAM memory compiler....
3533
0.118
Two Port Register File Compiler IP, UMC 0.25um process
UMC 0.25um Logic process synchronous Two Port Register File compiler....
3534
0.118
Two Port Register File Compiler IP, UMC 0.25um process
UMC 0.25um Logic process synchronous low density Low Power Two Port (1R1W) SRAM memory compiler....
3535
0.118
Two Port Register File Compiler IP, UMC 0.35um process
UMC 0.35um Logic process standard asynchronous low density Low Power Two Port (1R1W) SRAM memory compiler....
3536
0.118
Two Port Register File Compiler IP, UMC 0.35um process
UMC 0.35um Logic process synchronous high density Two Port (1R1W) SRAM memory compiler....
3537
0.118
Two Port Register File Compiler IP, UMC 0.35um process
UMC 0.35um Logic process synchronous high density Two Port (1R1W) SRAM memory compiler....
3538
0.118
Two Port Register File Compiler IP, UMC 0.35um process
UMC 0.35um Logic process synchronous low density Low Power Two Port (1R1W) SRAM memory compiler....
3539
0.118
Two Port Register File Compiler IP, UMC 0.35um process
UMC 0.35um Logic process synchronous low density Low Power Two Port (1R1W) SRAM memory compiler....
3540
0.118
Two Port Register File Compiler IP, UMC 0.35um process
UMC 0.35um Logic process standard asynchronous high density Two Port (1R1W) SRAM memory compiler....
3541
0.118
Two Port Register File Compiler IP, UMC 0.35um process
UMC 0.35um Logic process standard asynchronous high density Two Port (1R1W) SRAM memory compiler....
3542
0.118
Two Port Register File Compiler IP, UMC 0.35um process
UMC 0.35um Logic process standard asynchronous low density Low Power Two Port (1R1W) SRAM memory compiler....
3543
0.118
Two Port Register File Compiler IP, UMC 28nm HLP process
UMC 28nm HLP/ Low-K Two Port Register File compiler....
3544
0.118
Two Port Register File Compiler IP, UMC 28nm HLP process
UMC 28nm HLP peripheral LVT Two Port Register File memory compiler....
3545
0.118
Two Port Register File Compiler IP, UMC 40nm LP process
UMC 40nm LP/LVT process, Two Port Register File with LVT....
3546
0.118
Two Port Register File Compiler IP, UMC 40nm LP process
UMC 40nm LP Two Port Register File with Sleep/Retention/Nap mode feature....
3547
0.118
Two Port Register File Compiler IP, UMC 40nm LP process
UMC 40nm LP/RVT Low-K Logic Two Port Register File memory compiler....
3548
0.118
Two Port Register File Compiler IP, UMC 55nm LP process
UMC 55nm LP/ Low-K process PG Two Port Register File compiler....
3549
0.118
Two Port Register File Compiler IP, UMC 55nm LP process
UMC 55nm LP Logic process Synchronous Two Port Register File memory compiler....
3550
0.118
Two Port Register File Compiler IP, UMC 55nm SP process
UMC 55nm SP/RVT and HVT Low-K Logic process synchronous ultra high density/6T cell Two Port Register File memory compiler....