Design & Reuse
5044 IP
351
7.5
SDARC24 (Exclusively for Turnkey ASIC design; not for standalone licensing)
This is a 24-bit Sigma Delta ADC IP. This can take input signals < 10 kHz and converts them to digital form....
352
7.5
IEEE1284 Parallel Port Controller (Exclusively for Turnkey ASIC design; not for standalone licensing)
The IEEE1284 compliant parallel port controller supports faster data rates up to 2.0Mbytes/sec. It supports Nibble mode, Byte Mode, EPP, and ECP. Auto...
353
7.5
Temperature Sensor IP (Exclusively for Turnkey ASIC design; not for standalone licensing)
This is a Temperature Sensor IP. It measures temperature variations within the IC and converts them in to digital form. The processor in the system ca...
354
7.5
Generic GPIO Controller (Exclusively for Turnkey ASIC design; not for standalone licensing)
General Purpose I/O pins are used for system control and connection of various devices. This (GPIO) controller provides dedicated general-purpose pins...
355
7.5
Clock Management IP (Exclusively for Turnkey ASIC design; not for standalone licensing)
This is a Clock Management IP that can drive 3 different output clocks. These 3 different clocks are required for any simple Digital or Mixed Signal A...
356
7.5
Power Management IP (Exclusively for Turnkey ASIC design; not for standalone licensing)
This is a Power Management IP that can take 3 different input supplies and can drive 4 different output power domains. These 4 different power domains...
357
7.5
SPI Master/Slave Controller (Exclusively for Turnkey ASIC design; not for standalone licensing)
SPI Controller IP enables synchronous serial communication with slave or master peripherals. It has Generic interface which programs the control and d...
358
7.5
IrDA Controller (Exclusively for Turnkey ASIC design; not for standalone licensing)
The IRDA controller supports data rates from 2.4 Kbps to 115.2Kbps in SIR mode, 1.152 Mbps in MIR (Medium IR), and 4Mbps in FIR mode...
359
7.5
USB 2.0 Device controller (Exclusively for Turnkey ASIC design; not for standalone licensing)
USB 2.0 Device controller implements a complete high/full speed peripheral controller that interfaces UTMI USB port transceiver on one side and to an ...
360
7.5
USB 2.0 Host controller (Exclusively for Turnkey ASIC design; not for standalone licensing)
USB 2.0 Host Controller supports high (480 Mbps), full (12 Mbps) and low (1.5 Mbps) speed operation. Supports Control, Bulk, Isochronous and Interrupt...
361
7.5
USB 3.0 Device Controller (Exclusively for Turnkey ASIC design; not for standalone licensing)
USB3.0 Device Controller IP Core provides an integrated and customizable solution for USB3.0 Device applications. The Core is compliant with USB3.0/2....
362
7.5
USB 3.0 Host Controller (Exclusively for Turnkey ASIC design; not for standalone licensing)
USB3.0 Host Controller IP core provides an integrated and customizable solution for USB3.0 Host applications. The Core supports USB3.0/2.0 Specificati...
363
7.5
USB 3.0 Retimer (Exclusively for Turnkey ASIC design; not for standalone licensing)"
USB3.0 Retimer softcore is designed for use USB Port/Cable Retimer applications. The requirements set forth in the specification comprehend the use of...
364
7.5
Ethernet 10/100 MAC (Exclusively for Turnkey ASIC design; not for standalone licensing)
The Ethernet controller is compliant with IEEE802.3 and it provides an interface between the host subsystem and the Media Independent Interface (MII)....
365
6.0
SMART - DSMART - ISO 7816 Based Smart Card Reader
The DSMART is a fast, versatile and cost-competitive core intended for smart card reader applications. It provides a communication interface with a sm...
366
6.0
TurboConcept - SoC Design Services
IP Core profiling: We offer several profiles and scalability as part of our off-the shelf portfolio. Despite this large offering, you may have specif...
367
5.0
80251 - DQ80251 - Revolutionary Quad-Pipelined Ultra High Performance Microcontroller
The DQ80251 is a revolutionary Quad-Pipelined ultra high performance, speed optimized soft core of a 16-bit/32-bit embedded microcontroller. The core ...
368
5.0
I3C - DI3CM-HCI - MIPI I3C Basic v1.1.1 specifications with Host Controller Interface v1.1 specification
The I3C (Improved Inter-Integrated Circuit) is the successor of the I2C bus. Keeping the best assets from its elder brother, the I3C has major improve...
369
5.0
CAN 2.0, CAN FD - Developed as ISO26262-10 Safety Element out of Context (ISO26262 soft IP SEooC, ASIL-B ready design)
Introducing DCD’s Ingenious CAN FD IP Core: Empowering Engineers with Unparalleled Flexibility. When it comes to seamlessly infusing cutting-edge C...
370
5.0
DCRP1A - 100% Secure Cryptographic System for RSA, Diffie-Hellman and ECC with AMBA AHB, AXI4 and APB
The CryptOne, a 100% secure cryptographic system, has been based on more than 20 years DCD’s market experience. Starting from 1999, Digital Core Desig...
371
5.0
HDLC - DHDLC - HDLC/SDLC controller
The DHDLC IP core is used for controlling HDLC/SDLC transmission frame, designed to be used with 8-bit MCU, like DP8051/DP80390. It allows to save MCU...
372
5.0
AES - DAES XTS - Cryptographic co-processor for lightweight cryptography
DAES XTS IP Core from Digital Core Design is a compact cryptographic co-processor designed to seamlessly implement the Rijndael encryption algorithm i...
373
5.0
SHA - DSHA2-256 - SHA IP Core with native SHA2-256 HMAC support
The DSHA2-256 is a universal solution which efficiently accelerates SHA2-256 hash function compliant with FIPS PUB 180-4. It computes message digest i...
374
5.0
DMESCC - Enhanced Multiprotocol Serial Communication Controller
The DEMSCC – Dual channel Multiprotocol Enhanced Serial Communication Controller, is designed for use with 8- and 16- bit microprocessors. The DMESCC...
375
5.0
eSPI - DESPI - Enhanced Serial Peripheral Interface – Master/Slave with single, dual, and quad eSPI Bus support for Intel CPU’s
The DESPI is a fully configurable eSPI master/slave device supporting all features described in Enhanced Serial Peripheral Interface Base Specificatio...
376
5.0
UTS - DUTS - DCD's Universal Timers System
The DUTS stands for DCD’s Universal Timers System. It is a programmable and highly configurable device that comprises seven submodules: Pulse Width...
377
3.0
MAC - DMAC-RMII - 10/100 Mb Media Access Controller with RMII
Our innovative solution is a hardware implementation of media access control protocol defined by the IEEE standard. The DMAC-RMII in cooperation with ...
378
3.0
LIN - DLIN - LIN Bus Controller – Basic and Safety-Enhanced
DCD-SEMI believes that even though something may be small or slow, it can still offer maximal efficiency and ultimate reliability. That’s why our DLIN...
379
2.5
I2C Master
The MI2CM macro implements a synchronous single-chip I2C Master only Macro capable of linking one CPU to one I2C-bus. Communication with I2C-bus is ca...
380
2.5
I2C MAster Slave
The MI2CMS macro implements a synchronous single-chip I2C Master and Slave Macro capable of linking one CPU to one I2C-bus. Communication with I2C-bus...
381
2.5
I2C Slave
The MI2CS macro implements a synchronous single-chip I2C Slave Macro capable of linking one CPU to one I2C-bus. Communication with I2C-bus is carried ...
382
2.5
FAT32 IP Soft Core for NVMe
FAT32 IP Soft Core for NVMe...
383
2.5
SATA 2 HOST ON CYCLONE 5 GX
The LDS SATA 2 HOST_C5GX IP incorporates the Transport layer, the Link layer, the PHY layer and the Rate Match FIFO on a ALTERA Cyclone V GX FPGA. The...
384
2.5
SATA 3 Host Controller on ARRIA V FPGA
The LDS SATA 3 HOST AR5GX IP incorporates the Transport layer, the Link layer, the PHY layer and the Rate Macth FIFO on a ALTERA Stratix IV GX FPGA. T...
385
2.5
SATA 3 Host Controller on Xilinx Artix 7
The LDS SATA 3 HOST XA7 IP incorporates the Transport layer, the Link layer and the PHY layer on a Xilinx Artix 7 speed grade 2 FPGA. The LDS_SATA3_HO...
386
2.5
SATA 3 Host Controller on ZYNQ
The LDS SATA 3 HOST XZ7 IP incorporates the Transport layer, the Link layer and the PHY layer on a Xilinx Zynq speed grade 2 FPGA. The LDS SATA 3 HOST...
387
2.5
SATA 3 HOST IP on ARRIA 10 FPGA
The LDS-SATA3-HOST-A10GX IP incorporates the Transport layer, the Link layer, the PHY layer and the Rate Match FIFO on a INTEL ARRIA 10 GX FPGA. The L...
388
2.5
SATA Device Controller on Altera Arria II GX
The LDS SATA DEVICE AR2GX IP incorporates the Transport layer, the Link layer, the PHY layer and the Rate Macth FIFO on a ALTERA ARRIA II GX FPGA. The...
389
2.5
SATA Device Controller on Kintex 7
The LDS SATA 3 DEVICE XK7 IP incorporates the Command Layer, Transport layer, the Link layer and the PHY layer on a Xilinx Kintex 7 FPGA. The LDS SATA...
390
2.5
SATA Device on Stratix IV GX
The LDS SATA DEVICE STR4GX IP incorporates the Transport layer, the Link layer, the PHY layer and the Rate Macth FIFO on a ALTERA STRATIX IV GX FPGA. ...
391
2.5
SATA Device on Virtex 6
The LDS SATA DEVICE XV6 IP incorporates the Command Layer, Transport layer, the Link layer and the PHY layer on a Xilinx Virtex 6 FPGA. The LDS SATA D...
392
2.5
SATA HOST 3 ON KINTEX 7 Ultrascale
The LDS SATA 3 HOST XK7U IP incorporates the Transport layer, the Link layer and the PHY layer on a Xilinx Kintex 7 Ultrascale speed grade 2 FPGA. The...
393
2.5
SATA HOST 3 ON VIRTEX 7 GTH
...
394
2.5
SATA Host 6G Controller on Kintex 7
The LDS SATA 3 HOST XK7 IP incorporates the Transport layer, the Link layer and the PHY layer on a Xilinx Kintex 7 speed grade 2 FPGA. The LDS SATA 3 ...
395
2.5
SATA Host Controller
The LDS SATA HOST STR4GX IP incorporates the Transport layer, the Link layer, the PHY layer and the Rate Macth FIFO on a ALTERA Startix IV GX FPGA. Th...
396
2.5
SATA HOST Controller on Cyclone IV GX
The LDS SATA HOST C4GX IP incorporates the Transport layer, the Link layer, the PHY layer and the Rate Macth FIFO on a ALTERA Cyclone IV GX FPGA. The ...
397
2.5
SATA Host Controller on Spartan 6 LXT FPGA
The LDS SATA HOST SP6 IP incorporates the Transport layer, the Link layer and the PHY layer on a Xilinx Spartan 6 FPGA. The LDS SATA HOST SP6 IP is co...
398
2.5
SATA Host controller on Virtex 5 FXT
The LDS SATA HOST XF5 IP incorporates the Transport layer, the Link layer and the PHY layer on a Xilinx Virtex 5 FPGA. The LDS SATA HOST XV5 IP is com...
399
2.5
SATA Host Controller on Virtex 6 LXT
The LDS SATA HOST XV6 IP incorporates the Transport layer, the Link layer and the PHY layer on a Xilinx Virtex 6 FPGA. The LDS SATA HOST XV6 IP is com...
400
2.5
SATA Host on Altera Arria II GX
The LDS SATA HOST AR2GX IP incorporates the Transport layer, the Link layer, the PHY layer and the Rate Macth FIFO on a ALTERA ARRIA II GX FPGA. The L...