701 10.0

CAT Trip Sensor, TSMC N6 The Catastrophic Trip Sensor has been specifically designed to protect against thermal runaway and comprises a central hub and a remote thermal sensor...

702 10.0

WAVE521, H.265, HEVC, H.264, AVC video encoder IP for 4K WAVE521 is a 4K multi-format encoder IP to support both HEVC/H.265 and AVC/H.264 video formats. It is capable of encoding HEVC Main/Main 10/Main Sti...

703 10.0

WAVE521CL, H.265, HEVC, H.264, AVC video codec IP for 4K low-cost WAVE521CL is a low-cost 4K codec IP to support HEVC/H.265 and AVC/H.264 video standards. The codec IP is capable of encoding 4K60fps@500MHz with HEV...

704 10.0

WAVE521L, H.265, HEVC, H.264, AVC video encoder IP for 4K low-cost WAVE521L is a low-cost 4K encoder IP to support HEVC/H.265 and AVC/H.264 video standards. The IP core provides high-performance encode capability up t...

705 10.0

WAVE633LC, H.265, HEVC, H.264, AVC, video codec IP for 4K low-cost WAVE633LC is a 4K multi-standard video codec IP that supports HEVC/H.265 and AVC/H.264 video codec standards. WAVE633LC targets Low Cost, so B-frame i...

706 10.0

HBM3 Controller IP is optimized for power, latency, bandwidth, and area, supporting the JEDEC HBM3 standard Synopsys HBM3 Controller IP is optimized for power, latency, bandwidth, and area, supporting the JEDEC HBM3 standard. The controller interoperates wit...

707 10.0

HBM3 PHY IP at 7nm OPENEDGES, the memory system IP provider, including DDR memory controller, DDR PHY, on-chip interconnect, and NPU IP together as an integrated solutio...

708 10.0

PCI Express GEN 3/4 Port SERDES PHY - Samsung 14LPP Analog Bits Programmable SERDES provides a Physical Media Attachment (PMA) Layer capable of signaling at multiple data rates and supports multi-protoc...

709 10.0

PCI Express GEN 3/4 Port SERDES PHY - Samsung 7LPP Analog Bits Programmable SERDES provides a Physical Media Attachment (PMA) Layer and synthesizable Physical Coding Sublayer (PCS). The integrated PHY ...

710 10.0

PCI Express GEN 4/5 Port SERDES PHY - Samsung 8LPP Analog Bits Programmable SERDES provides a Physical Media Attachment (PMA) Layer and synthesizable Physical Coding Sublayer (PCS). The integrated PHY ...

711 10.0

PCI Express GEN-3/Display Port SERDES PHY - Samsung 28 28LPP Analog Bits Programmable SERDES provides a Physical Media Attachment (PMA) Layer capable of signaling at multiple data rates and supports multi-protoc...

712 10.0

PCI Express GEN-3/SATA3 SERDES PHY - Samsung 28 28FDSOI Analog Bits Programmable SERDES provides a Physical Media Attachment (PMA) Layer capable of signaling at multiple data rates and supports multi-protoc...

713 10.0

PCIe 4.0 LP PHY in TSMC (N7) for Automotive The multi-channel Synopsys PHY IP for PCI Express® 4.0 includes Synopsys’ high-speed, high-performance transceiver to meet today’s applications’ deman...

714 10.0

PCIe 4/5 Refenece Clock PLL with SSCS - GLOBALFOUNDRIES 12LP+ Analog Bits’ Programmable SERDES provides a Physical Media Attachment (PMA) Layer and synthesizable Physical Coding Sublayer (PCS). The integrated PHY...

715 10.0

PCIe 5.0 PHY NCS in TSMC (N7, N6, N6C, N5) The multi-channel Synopsys PHY IP for PCI Express® 5.0 and CXL includes Synopsys’ high-speed, high-performance transceiver to meet today’s applicatio...

716 10.0

PCIe Gen 4/5/6 Ref Clock SSCG PLL - TSMC CLN2P Analog Bits’ PCIe REF PLL addresses stringent performance requirements in high-speed serial link applications that support the PCI Express Gen4 and Ge...

717 10.0

PCIe Gen 4/5/6 Ref Clock SSCG PLL - TSMC CLN7FF Analog Bits’ PCIe REF PLL addresses stringent performance requirements in high-speed serial link applications that support the PCI Express Gen4 and Ge...

718 10.0

PCIe Gen4/5 Ref SSCG PLL - TSMC CLN3A Analog Bits’ PCIe REF PLL addresses stringent performance requirements in high-speed serial link applications that support the PCI Express Gen4 and Ge...

719 10.0

PCIe Gen4/5 Ref SSCG PLL - TSMC CLN3E Analog Bits’ PCIe REF PLL addresses stringent performance requirements in high-speed serial link applications that support the PCI Express Gen4 and Ge...

720 10.0

PCIe/HCSL Differential IO Buffer - TSMC 16FFC Analog Bits offers a unique set of IP's that is used for various SERDES applications. This unique IP is used for sending source clocks to SERDES for P...

721 10.0

PCIe3 SSCG PLL - GLOBALFOUNDRIES 12LP Analog Bits’ PCIe Gen3 SSCG PLL addresses stringent performance requirements in high-speed serial link applications that support the PCI Express Gen3 ...

722 10.0

PCIe3 SSCG PLL - GLOBALFOUNDRIES 12LP+ Analog Bits’ PCIe Gen3 SSCG PLL addresses stringent performance requirements in high-speed serial link applications that support the PCI Express Gen3 ...

723 10.0

PCIe3 SSCG PLL - TSMC 12FFC Analog Bits’ Programmable SERDES provides a Physical Media Attachment (PMA) Layer and synthesizable Physical Coding Sublayer (PCS). The integrated PHY...

724 10.0

PCIe3 SSCG PLL - TSMC 16FFC Analog Bits’ PCIe Gen3 SSCG PLL addresses stringent performance requirements in high-speed serial link applications that support the PCI Express Gen3 ...

725 10.0

PCIe4 Ethernet SERDES PHY - TSMC N5 Analog Bits’ Programmable SERDES provides a Physical Media Attachment (PMA) Layer and synthesizable Physical Coding Sublayer (PCS). The integrated PHY...

726 10.0

PCIe5 Ref Clock SSCG PLL - TSMC 6FF Analog Bits’ PCIe Gen 5 Ref Clock SSCG PLL addresses stringent performance requirements in high-speed serial link applications that support the PCI Ex...

727 10.0

SD 3.0 / SDIO 3.0 Combo Device Controller The SD / SDIO 3.0 Combo Device IP Core is a high performance controller capable of interfacing with memory cards and I/O applications such as WLAN, Bl...

728 10.0

SD 4.0 Device Controller The SD 4.0 Device IP core is used to implement SD cards connected to a Host processor over standard SD bus. The flexible architecture of SD Device IP ...

729 10.0

SD 4.1 SDIO 4.1 Host Controller IP The SD 4.1/SDIO 4.1 IP from Arasan Chip Systems is a highly integrated host controller IP solution that supports two key memory card I/O technologies:...

730 10.0

SD 6.0 UHS-III PHY Silicon Library's world-first silicon proven UHS-III PHY is available in SMIC 65 now....

731 10.0

SD/eMMC in GF (12nm) To address today’s content capacity and bandwidth requirements, JEDEC and SD Association continue to define new functionality and enhancements for emb...

732 10.0

SD/eMMC in TSMC (28nm, 16nm, 12nm, N7, N6) To address today’s content capacity and bandwidth requirements, JEDEC and SD Association continue to define new functionality and enhancements for emb...

733 10.0

GDDR6 Memory Controller IP OPENEDGES, the memory system IP provider, including DDR memory controller, DDR PHY, on-chip interconnect, and NPU IP together as an integrated solutio...

734 10.0

GDDR6 PHY IP for 12nm OPENEDGES, the memory system IP provider, including DDR memory controller, DDR PHY, on-chip interconnect, and NPU IP together as an integrated solutio...

735 10.0

SDIO 3.0 Device Controller Arasan's SDIO 3.0 Device IP is used to implement high-performance SDIO cards that connect to a Host processor over a standard SD bus. The SDIO 3.0 Dev...

736 10.0

HDMI 1.4b RX LINK with HDCP 1.4 Silicon Library's HDMI 1.4b RX Link IP is the best choice for our PHY IPs. HDCP 1.4 is included and customer-requested features can be added....

737 10.0

HDMI 1.4b TX LINK with HDCP 1.4 Silicon Library's HDMI 1.4b TX Link IP is the best choice for our PHY IPs. HDCP 1.4 is included and customer-requeted features can be added....

738 10.0

HDMI 2.0 RX LINK with HDCP 2.2 Silicon Library's HDMI 2.0 RX Link IP is the best choice for our PHY IPs. HDCP 2.2 is included and customer-requested features can be added....

739 10.0

HDMI 2.0 TX LINK with HDCP 2.2 Silicon Library's HDMI 2.0 TX Link IP is the best choice for our PHY IPs. HDCP 2.2 is included and customer-requested features can be added....

740 10.0

LDO for CPU Cores - TSMC CLN3A ...

741 10.0

LDO for CPU Cores - TSMC CLN3E ...

742 10.0

DDR and LPDDR 5/4/3/2 controllers for low power and high Reliability, Availability and Serviceability (RAS) Synopsys offers a complete system-level memory interface IP portfolio for SoCs requiring an interface to one or a range of high-performance DDR5, DDR4...

743 10.0

DDR and LPDDR 5/4/3/2 controllers for low power and high Reliability, Availability and Serviceability (RAS) targeting automotive Synopsys offers a complete system-level memory interface IP portfolio for SoCs requiring an interface to one or a range of high-performance DDR5, DDR4...

744 10.0

DDR2/DDR3/DDR3L/LPDDR2 I/O Buffer - TSMC 40 CLN40LP Analog Bits impedance programmable I/O buffer provides a high-speed physical interface solution to support the increasing bandwidths demanded by today...

745 10.0

DDR4 multiPHY in Samsung (14nm) The Synopsys DDR4 multiPHY is a complete physical (PHY) layer IP interface solution for PC/consumer and mobile ASICs, ASSPs, system-on- chip (SoC), an...

746 10.0

DDR4 multiPHY in TSMC (28nm) The Synopsys DDR4 multiPHY is a complete physical (PHY) layer IP interface solution for PC/consumer and mobile ASICs, ASSPs, system-on- chip (SoC), an...

747 10.0

DDR4 multiPHY in UMC (28nm) The Synopsys DDR4 multiPHY is a complete physical (PHY) layer IP interface solution for PC/consumer and mobile ASICs, ASSPs, system-on- chip (SoC), an...

748 10.0

DDR4/3 PHY in Samsung (14nm, 11nm, 10nm, 8nm) The Synopsys DDR4/3 PHY is a complete physical layer IP interface (PHY) solution for enterprise-class ASIC, ASSP, and system-on-chip (SoC) application...

749 10.0

DDR4/3 PHY in TSMC (12nm, 16nm, 7nm) The Synopsys DDR4/3 PHY is a complete physical layer IP interface (PHY) solution for enterprise-class ASIC, ASSP, and system-on-chip (SoC) application...

750 10.0

DDR5 PHY in Samsung (SF4X) The Synopsys DDR5/4 PHY is a complete physical layer IP interface (PHY) solution for ASIC, ASSP, and system-on-chip (SoC) applications requiring high-...