Design & Reuse
Catalog of SIP Cores
System on Chip design resources
5506 IP
1151
10.0
CAT Trip Sensor, TSMC N3
The Catastrophic Trip Sensor has been specifically designed to protect against thermal runaway and comprises a central hub and a remote thermal sensor...
1152
10.0
CAT Trip Sensor, TSMC N3EP
The Catastrophic Trip Sensor has been specifically designed to protect against thermal runaway and comprises a central hub and a remote thermal sensor...
1153
10.0
CAT Trip Sensor, TSMC N5
The Catastrophic Trip Sensor has been specifically designed to protect against thermal runaway and comprises a central hub and a remote thermal sensor...
1154
10.0
CAT Trip Sensor, TSMC N6
The Catastrophic Trip Sensor has been specifically designed to protect against thermal runaway and comprises a central hub and a remote thermal sensor...
1155
10.0
WAVE521, H.265, HEVC, H.264, AVC video encoder IP for 4K
WAVE521 is a 4K multi-format encoder IP to support both HEVC/H.265 and AVC/H.264 video formats. It is capable of encoding HEVC Main/Main 10/Main Sti...
1156
10.0
WAVE521CL, H.265, HEVC, H.264, AVC video codec IP for 4K low-cost
WAVE521CL is a low-cost 4K codec IP to support HEVC/H.265 and AVC/H.264 video standards. The codec IP is capable of encoding 4K60fps@500MHz with HEV...
1157
10.0
WAVE521L, H.265, HEVC, H.264, AVC video encoder IP for 4K low-cost
WAVE521L is a low-cost 4K encoder IP to support HEVC/H.265 and AVC/H.264 video standards. The IP core provides high-performance encode capability up t...
1158
10.0
WAVE633LC, H.265, HEVC, H.264, AVC, video codec IP for 4K low-cost
WAVE633LC is a 4K multi-standard video codec IP that supports HEVC/H.265 and AVC/H.264 video codec standards. WAVE633LC targets Low Cost, so B-frame i...
1159
10.0
HBM3 Controller IP is optimized for power, latency, bandwidth, and area, supporting the JEDEC HBM3 standard
Synopsys HBM3 Controller IP is optimized for power, latency, bandwidth, and area, supporting the JEDEC HBM3 standard. The controller interoperates wit...
1160
10.0
HBM3 PHY IP at 7nm
OPENEDGES, the memory system IP provider, including DDR memory controller, DDR PHY, on-chip interconnect, and NPU IP together as an integrated solutio...
1161
10.0
PCI Express GEN 3/4 Port SERDES PHY - Samsung 14LPP
Analog Bits Programmable SERDES provides a Physical Media Attachment (PMA) Layer capable of signaling at multiple data rates and supports multi-protoc...
1162
10.0
PCI Express GEN 3/4 Port SERDES PHY - Samsung 7LPP
Analog Bits Programmable SERDES provides a Physical Media Attachment (PMA) Layer and synthesizable Physical Coding Sublayer (PCS). The integrated PHY ...
1163
10.0
PCI Express GEN 4/5 Port SERDES PHY - Samsung 8LPP
Analog Bits Programmable SERDES provides a Physical Media Attachment (PMA) Layer and synthesizable Physical Coding Sublayer (PCS). The integrated PHY ...
1164
10.0
PCI Express GEN-3/Display Port SERDES PHY - Samsung 28 28LPP
Analog Bits Programmable SERDES provides a Physical Media Attachment (PMA) Layer capable of signaling at multiple data rates and supports multi-protoc...
1165
10.0
PCI Express GEN-3/SATA3 SERDES PHY - Samsung 28 28FDSOI
Analog Bits Programmable SERDES provides a Physical Media Attachment (PMA) Layer capable of signaling at multiple data rates and supports multi-protoc...
1166
10.0
PCIe 4.0 LP PHY in TSMC (N7) for Automotive
The multi-channel Synopsys PHY IP for PCI Express® 4.0 includes Synopsys’ high-speed, high-performance transceiver to meet today’s applications’ deman...
1167
10.0
PCIe 4/5 Refenece Clock PLL with SSCS - GLOBALFOUNDRIES 12LP+
Analog Bits’ Programmable SERDES provides a Physical Media Attachment (PMA) Layer and synthesizable Physical Coding Sublayer (PCS). The integrated PHY...
1168
10.0
PCIe 5.0 PHY NCS in TSMC (N7, N6, N6C, N5, N3P)
The multi-channel Synopsys PHY IP for PCI Express® 5.0 and CXL includes Synopsys’ high-speed, high-performance transceiver to meet today’s applicatio...
1169
10.0
PCIe Gen 4/5/6 Ref Clock SSCG PLL - TSMC CLN2P
Analog Bits’ PCIe REF PLL addresses stringent performance requirements in high-speed serial link applications that support the PCI Express Gen4 and Ge...
1170
10.0
PCIe Gen 4/5/6 Ref Clock SSCG PLL - TSMC CLN7FF
Analog Bits’ PCIe REF PLL addresses stringent performance requirements in high-speed serial link applications that support the PCI Express Gen4 and Ge...
1171
10.0
PCIe Gen4/5 Ref SSCG PLL - TSMC CLN3A
Analog Bits’ PCIe REF PLL addresses stringent performance requirements in high-speed serial link applications that support the PCI Express Gen4 and Ge...
1172
10.0
PCIe Gen4/5 Ref SSCG PLL - TSMC CLN3E
Analog Bits’ PCIe REF PLL addresses stringent performance requirements in high-speed serial link applications that support the PCI Express Gen4 and Ge...
1173
10.0
PCIe/HCSL Differential IO Buffer - TSMC 16FFC
Analog Bits offers a unique set of IP's that is used for various SERDES applications. This unique IP is used for sending source clocks to SERDES for P...
1174
10.0
PCIe3 SSCG PLL - GLOBALFOUNDRIES 12LP
Analog Bits’ PCIe Gen3 SSCG PLL addresses stringent performance requirements in high-speed serial link applications that support the PCI Express Gen3 ...
1175
10.0
PCIe3 SSCG PLL - GLOBALFOUNDRIES 12LP+
Analog Bits’ PCIe Gen3 SSCG PLL addresses stringent performance requirements in high-speed serial link applications that support the PCI Express Gen3 ...
1176
10.0
PCIe3 SSCG PLL - TSMC 12FFC
Analog Bits’ Programmable SERDES provides a Physical Media Attachment (PMA) Layer and synthesizable Physical Coding Sublayer (PCS). The integrated PHY...
1177
10.0
PCIe3 SSCG PLL - TSMC 16FFC
Analog Bits’ PCIe Gen3 SSCG PLL addresses stringent performance requirements in high-speed serial link applications that support the PCI Express Gen3 ...
1178
10.0
PCIe4 Ethernet SERDES PHY - TSMC N5
Analog Bits’ Programmable SERDES provides a Physical Media Attachment (PMA) Layer and synthesizable Physical Coding Sublayer (PCS). The integrated PHY...
1179
10.0
PCIe5 Ref Clock SSCG PLL - TSMC 6FF
Analog Bits’ PCIe Gen 5 Ref Clock SSCG PLL addresses stringent performance requirements in high-speed serial link applications that support the PCI Ex...
1180
10.0
SD 6.0 UHS-III PHY
Silicon Library's world-first silicon proven UHS-III PHY is available in SMIC 65 now....
1181
10.0
SD/eMMC in GF (12nm)
To address today’s content capacity and bandwidth requirements, JEDEC and SD Association continue to define new functionality and enhancements for emb...
1182
10.0
SD/eMMC in TSMC (28nm, 16nm, 12nm, N7, N6)
To address today’s content capacity and bandwidth requirements, JEDEC and SD Association continue to define new functionality and enhancements for emb...
1183
10.0
GDDR6 PHY IP for 12nm
OPENEDGES, the memory system IP provider, including DDR memory controller, DDR PHY, on-chip interconnect, and NPU IP together as an integrated solutio...
1184
10.0
HDMI 1.4b RX LINK with HDCP 1.4
Silicon Library's HDMI 1.4b RX Link IP is the best choice for our PHY IPs. HDCP 1.4 is included and customer-requested features can be added....
1185
10.0
HDMI 1.4b TX LINK with HDCP 1.4
Silicon Library's HDMI 1.4b TX Link IP is the best choice for our PHY IPs. HDCP 1.4 is included and customer-requeted features can be added....
1186
10.0
HDMI 2.0 RX LINK with HDCP 2.2
Silicon Library's HDMI 2.0 RX Link IP is the best choice for our PHY IPs. HDCP 2.2 is included and customer-requested features can be added....
1187
10.0
HDMI 2.0 TX LINK with HDCP 2.2
Silicon Library's HDMI 2.0 TX Link IP is the best choice for our PHY IPs. HDCP 2.2 is included and customer-requested features can be added....
1188
10.0
LDO for CPU Cores - TSMC CLN3A
...
1189
10.0
LDO for CPU Cores - TSMC CLN3E
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1190
10.0
DDR and LPDDR 5/4/3/2 controllers for low power and high Reliability, Availability and Serviceability (RAS)
Synopsys offers a complete system-level memory interface IP portfolio for SoCs requiring an interface to one or a range of high-performance DDR5, DDR4...
1191
10.0
DDR and LPDDR 5/4/3/2 controllers for low power and high Reliability, Availability and Serviceability (RAS) targeting automotive
Synopsys offers a complete system-level memory interface IP portfolio for SoCs requiring an interface to one or a range of high-performance DDR5, DDR4...
1192
10.0
DDR2/DDR3/DDR3L/LPDDR2 I/O Buffer - TSMC 40 CLN40LP
Analog Bits impedance programmable I/O buffer provides a high-speed physical interface solution to support the increasing bandwidths demanded by today...
1193
10.0
DDR4 multiPHY in Samsung (14nm)
The Synopsys DDR4 multiPHY is a complete physical (PHY) layer IP interface solution for PC/consumer and mobile ASICs, ASSPs, system-on- chip (SoC), an...
1194
10.0
DDR4 multiPHY in TSMC (28nm)
The Synopsys DDR4 multiPHY is a complete physical (PHY) layer IP interface solution for PC/consumer and mobile ASICs, ASSPs, system-on- chip (SoC), an...
1195
10.0
DDR4 multiPHY in UMC (28nm)
The Synopsys DDR4 multiPHY is a complete physical (PHY) layer IP interface solution for PC/consumer and mobile ASICs, ASSPs, system-on- chip (SoC), an...
1196
10.0
DDR4/3 PHY in Samsung (14nm, 11nm, 10nm, 8nm)
The Synopsys DDR4/3 PHY is a complete physical layer IP interface (PHY) solution for enterprise-class ASIC, ASSP, and system-on-chip (SoC) application...
1197
10.0
DDR4/3 PHY in TSMC (12nm, 16nm, 7nm)
The Synopsys DDR4/3 PHY is a complete physical layer IP interface (PHY) solution for enterprise-class ASIC, ASSP, and system-on-chip (SoC) application...
1198
10.0
DDR5 PHY in Samsung (SF2, SF4X)
The Synopsys DDR5/4 PHY is a complete physical layer IP interface (PHY) solution for ASIC, ASSP, and system-on-chip (SoC) applications requiring high-...
1199
10.0
DDR5/4 PHY in GF (12nm)
The Synopsys DDR5/4 PHY is a complete physical layer IP interface (PHY) solution for ASIC, ASSP, and system-on-chip (SoC) applications requiring high-...
1200
10.0
DDR5/4 PHY in Samsung (10nm, 8nm, 7nm)
The Synopsys DDR5/4 PHY is a complete physical layer IP interface (PHY) solution for ASIC, ASSP, and system-on-chip (SoC) applications requiring high-...