Design & Reuse
970 IP
951
0.0
PVCI (Peripheral VCI) Verification IP
PVCI Verification IP provides an smart way to verify the PVCI component of a SOC or a ASIC. The SmartDV s PVCI Verification IP is fully compliant with...
952
0.0
NVDIMM-P Memory Model
NVDIMM P Memory Model provides an smart way to verify the NVDIMM P component of a SOC or a ASIC. The SmartDV s NVDIMM P memory model is fully complian...
953
0.0
AVSBUS Master IP
SmartDV’s AVSBus Master IP is a silicon-proven solution designed to enable efficient, high-speed communication between power management controllers an...
954
0.0
AVSBUS Slave IP
SmartDV’s AVSBus Slave IP is a silicon-proven solution designed for efficient power management communication between digital controllers and voltage r...
955
0.0
SWD (Serial Wire Debug) Verification IP
SWD(Serial Wire Debug) Verification IP provides an efficient and simple way to debug and trace functionality on processor cores and System on Chip (So...
956
0.0
Twin Quad NOR Flash Memory Model
Twin Quad NOR Flash Memory Model provides an smart way to verify the Twin Quad NOR Flash component of a SOC or a ASIC. The SmartDV s Twin Quad NOR Fla...
957
0.0
SWP (Single Wire Protocol) Verification IP
SWP Verification IP is a smart way to verify the SWP component of a SOC or ASIC. The SmartDV s SWP Verification IP is fully compliant with standard ET...
958
0.0
Excelon FRAM Memory Model
Excelon FRAM Memory Model provides an smart way to verify the Excelon FRAM component of a SOC or a ASIC. The SmartDV s Excelon FRAM memory model is fu...
959
0.0
AXI Multilayer Interconnect IP
SmartDV’s AXI Multilayer Interconnect IP is a high-throughput, silicon-proven solution designed to manage complex on-chip communication between multip...
960
0.0
AXI to AHB Bridge IP
SmartDV’s AXI to AHB Bridge IP enables seamless interoperability between AMBA AXI and AMBA AHB protocols, allowing efficient data transfer across syst...
961
0.0
AXI to APB Bridge IP
SmartDV’s AXI to APB Bridge IP enables seamless communication between high-performance AXI-based systems and simpler, lower-power APB peripherals. It ...
962
0.0
AXI to UCIe Bridge IP
SmartDV’s AXI to UCIe Bridge IP enables seamless integration between standard AMBA AXI-based SoC architectures and the emerging UCIe (Universal Chiple...
963
0.0
CXL 1.x Controller IP
SmartDV’s CXL (Compute Express Link) 1.x Controller IP enables high-speed, low-latency, and cache-coherent communication between CPUs, memory, and acc...
964
0.0
CXL 2.x Controller IP
SmartDV’s CXL (Compute Express Link) 2.0 Controller IP extends support for advanced memory pooling, switching, and persistent memory, enhancing scalab...
965
0.0
CXL 3.x Controller IP
SmartDV’s CXL (Compute Express Link) 3.x Controller IP brings high-speed, coherent connectivity with enhanced fabric capabilities—supporting memory-ce...
966
0.0
CXL to UCIe Bridge IP
SmartDV’s CXL to UCIe Bridge IP enables seamless interoperability between Compute Express Link (CXL) and Universal Chiplet Interconnect Express (UCIe)...
967
0.0
CXP Host IP
SmartDV’s CXP (CoaXPress) Host IP is a high-performance solution designed for machine vision, industrial inspection, and high-speed imaging applicatio...
968
0.0
CXS to UCIe Bridge IP
SmartDV’s CXS to UCIe Bridge IP enables seamless connectivity between chiplet-based designs and traditional SoC architectures by bridging AMBA CXS int...
969
0.0
HyperFlash Memory Model
HyperFlash Memory Model provides an smart way to verify the HyperFlash component of a SOC or a ASIC. The SmartDV s HyperFlash memory model is fully co...
970
0.0
HyperRAM Memory Model
HyperRAM Memory Model provides an smart way to verify the HyperRAM component of a SOC or a ASIC. The SmartDV s HyperRAM memory model is fully complian...