Design & Reuse
1932 IP
751
5.0
1:6 Fixed Length Visually Lossless Compression/Decompression
Suppressing the degradation of image quality by the original comp./decomp. processing, drastic reductions of Memory amount and Bandwidth could be real...
752
5.0
SAS 4 Port 12G Recorder
The SAS Recorder IP Core provides an ready to use solution for high speed data recording applications. Simple interface guarantees fast time to marke...
753
5.0
SAS Initiator, 12G, 4 Ports, 48 Gbps, SATA Host
The SAS Initiator Controller IP Core provides an interface to high-speed serial link replacement for the parallel SCSI attachment of mass storage devi...
754
5.0
SATA Device IP Core (1.5, 3.0, 6.0 Gbps)
The Serial ATA Device Controller IP Core provides an interface to high-speed serial link replacements for the parallel ATA attachment of mass storage ...
755
5.0
DDI Color Enhancement (CLREN) IP
BTREE's Color Enhancement IP modifies or emphasizes color by controlling Saturation/Luminance/Hue. BTREE's Color Enhancement can only adjust the color...
756
5.0
DDI High Dynamic Range IP
HDR improves the visibility of the output image compared to the input images by increasing the contrast of the image/video reproduced on the display. ...
757
5.0
Serial ATA Host Controller (1.5, 3.0, 6.0 Gb/s)
The Serial ATA Host IP Core provides an interface to high-speed serial link replacements for the parallel ATA attachment of mass storage devices. The ...
758
5.0
Serial ATA Host Controller (1.5, 3.0, 6.0 Gb/s) for Xilinx UltraScale
The Serial ATA Host IP Core provides an interface to high-speed serial link replacements for the parallel ATA attachment of mass storage devices. The ...
759
5.0
Visually LossLess compression hardware RTL core that complies with ISO/IEC-21122-1 (JPEG XS)
TMC’s JPEG XS encoder / decoder IP is Visually LossLess compression / decompression hardware RTL core that complies with ISO/IEC-21122-1 (JPEG XS). T...
760
5.0
Visually LossLess decompression hardware RTL core that complies with ISO/IEC-21122-1 (JPEG XS)
TMC’s JPEG XS encoder / decoder IP is Visually LossLess decompression hardware RTL core that complies with ISO/IEC-21122-1 (JPEG XS). The logic gate ...
761
5.0
Compact LossLess Decoder RTL Core
...
762
5.0
Compact LossLess Encoder RTL Core
...
763
5.0
Lossless / Near lossless Encoder / Decoder Hardware IP
- Lossless / near lossless hardware encoder and decoder IP that features compact and high speed with TMC original algorithm. - Optimized logic gate...
764
5.0
JPEG Decoder 1-pixel/clock
- Baseline JPEG encoder/decoder described in RTL compliant with ISO/IEC 10918-1 - High speed processing with low clock frequency - Suitable for ...
765
5.0
JPEG Encoder 1-pixel/clock
- Baseline JPEG encoder/decoder described in RTL compliant with ISO/IEC 10918-1 - High speed processing with low clock frequency - Suitable for ...
766
5.0
Frame Rate Converter for 4K
TMC’s FRUC (Frame Rate Up-Converter) for 4K RTL Core utilizes proprietary ”DMNA- MEMC” (Motion Estimation and Motion Compensation) algorithm which gen...
767
4.0
DDI Scaler IP - BSCALE
BTREE’s BSCALE enlarges or reduces the input video to fit the panel size. Polynomial Interpolation (PI) is the basic algorithm, and also various metho...
768
4.0
DDI Scaler IP - MSCALE
BTREE’s MSCALE enlarges the input video to fit the panel size. Bi-Linear interpolation is the basic algorithm, and also various methods such as sharpn...
769
4.0
Reed Solomon Decoder IP Core
A high performance, fully configurable Reed Solomon Decoder IP Core that is intended for use in a wide range of applications requiring forward error c...
770
4.0
Reed Solomon Encoder IP Core
A high performance, fully configurable Reed Solomon Encoder IP Core that is intended for use in a wide range of applications requiring forward error c...
771
3.0
High Performance, Low Latency PCIe Gen5 PHY
Terminus Circuits offers best-in-class PHY IP for PCI Express Gen 5/4/3/2/1. The PHY is designed for low latency, low power, small form factor, high i...
772
3.0
High Speed Low Jitter 16GHz Output LC PLL
Terminus Circuits offers an Analog Phase Locked Loop which is a LC oscillator-based integer-N PLL IP powered at 900 mV. The PLL operates with input re...
773
3.0
Single Lane and Quad Lane 10Gbps USB3.1 PHY IP in GF 28SLP process
TERMINUS CIRCUITS USB 3.1 GEN2 PHY is high performance, low power, low latency Single & Quad-Lane PHY that supports USB protocol and its signalling ne...
774
3.0
Single Lane and Quad Lane 10Gbps USB3.1 PHY IP in TSMC 28HPC process
TERMINUS CIRCUITS USB 3.1 GEN2 PHY is high performance, low power, low latency Single & Quad-Lane PHY that supports USB protocol and its signalling ne...
775
3.0
Single Lane and Quad Lane 10Gbps USB3.1 PHY IP in TSMC 55LP process
TERMINUS CIRCUITS USB 3.1 GEN2 PHY is high performance, low power, low latency Single & Quad-Lane PHY that supports USB protocol and its signalling ne...
776
3.0
Single Lane and Quad Lane 10Gbps USB3.1 PHY IP in TSMC 65GP process
TERMINUS CIRCUITS USB 3.1 GEN2 PHY is high performance, low power, low latency Single & Quad-Lane PHY that supports USB protocol and its signalling ne...
777
3.0
Single Lane and Quad Lane 16Gbps PCIe4.0 PHY IP in TSMC 28HPC process
TERMINUS CIRCUITS PCIe GEN4.0 PHY is high performance, low power, low latency Single & Quad-Lane PCI Express PHY that supports PCI Express protocol an...
778
3.0
Single Lane and Quad Lane 5Gbps PCIe2.0 PHY IP in GF 28SLP process
TERMINUS CIRCUITS PCIe GEN2.0 PHY is high performance, low power, low latency Single & Quad-Lane PCI Express PHY that supports PCI Express protocol a...
779
3.0
Single Lane and Quad Lane 5Gbps PCIe2.0 PHY IP in TSMC 28HPC process
TERMINUS CIRCUITS PCIe GEN2.0 PHY is high performance, low power, low latency Single & Quad-Lane PCI Express PHY that supports PCI Express protocol an...
780
3.0
Single Lane and Quad Lane 5Gbps PCIe2.0 PHY IP in TSMC 55LP process
TERMINUS CIRCUITS PCIe GEN2.0 PHY is high performance, low power, low latency Single & Quad-Lane PCI Express PHY that supports PCI Express protocol an...
781
3.0
Single Lane and Quad Lane 5Gbps PCIe2.0 PHY IP in TSMC 65GP process
TERMINUS CIRCUITS PCIe GEN2.0 PHY is high performance, low power, low latency Single & Quad-Lane PCI Express PHY that supports PCI Express protocol an...
782
3.0
Single Lane and Quad Lane 5Gbps USB3.1 PHY IP in GF 28SLP process
TERMINUS CIRCUITS USB 3.1 GEN1 PHY is high performance, low power, low latency Single & Quad-Lane PHY that supports USB protocol and its signalling ne...
783
3.0
Single Lane and Quad Lane 5Gbps USB3.1 PHY IP in TSMC 28HPC process
TERMINUS CIRCUITS USB 3.1 GEN1 PHY is high performance, low power, low latency Single & Quad-Lane PHY that supports USB protocol and its signalling ne...
784
3.0
Single Lane and Quad Lane 5Gbps USB3.1 PHY IP in TSMC 55LP process
TERMINUS CIRCUITS USB 3.1 GEN1 PHY is high performance, low power, low latency Single & Quad-Lane PHY that supports USB protocol and its signalling ne...
785
3.0
Single Lane and Quad Lane 5Gbps USB3.1 PHY IP in TSMC 65GP process
TERMINUS CIRCUITS USB 3.1 GEN1 PHY is high performance, low power, low latency Single & Quad-Lane PHY that supports USB protocol and its signalling ne...
786
3.0
Single Lane and Quad Lane 8Gbps PCIe3.0 PHY in Samsung 28LPP process
TERMINUS CIRCUITS PCIe GEN3.0 PHY is high performance, low power, low latency Single & Quad-Lane PCI Express PHY that supports PCI Express protocol an...
787
3.0
Single Lane and Quad Lane 8Gbps PCIe3.0 PHY IP in GF 28SLP process
TERMINUS-CIRCUITS PCIe GEN3.0 PHY is high performance, low power, low latency Single &Quad-Lane PCI Express PHY that supports PCI Express protocol and...
788
3.0
Single Lane and Quad Lane 8Gbps PCIe3.0 PHY IP in TSMC 28HPC process
TERMINUS CIRCUITS PCIe GEN3.0 PHY is high performance, low power, low latency Single & Quad-Lane PCI Express PHY that supports PCI Express protocol an...
789
3.0
Single Lane and Quad Lane 8Gbps PCIe3.0 PHY IP in TSMC 65G process
TERMINUS CIRCUITS PCIe GEN3.0 PHY is high performance, low power, low latency Single & Quad-Lane PCI Express PHY that supports PCI Express protocol an...
790
3.0
MIPI 4.1 M-PHY HS Gear 4
MIPI M-PHY HS Gear 4 IP is compliant with the MIPI serial communication protocol for use in mobile systems where performance, power, and efficiency ar...
791
3.0
Low Jitter 1.25GHz to 2.5GHz Quadrature Output PLL
Terminus Circuits offers High speed, low Jitter PLL with 1.25GHz to 2.5GHz output. The ring oscillator based PLL provides balanced quadrature output. ...
792
3.0
USB 2.0 (LS, FS & HS) On-The-Go IP Core
A 'Dual-Role' USB On-The-Go IP Core that operates as both an USB peripheral or as an USB OTG host in a point-to-point communications with another USB ...
793
3.0
Multi-Link Multi-Protocol SerDes 10Gbps in GF 28SLP
Terminus Circuits offers low power, low latency Multistandard SerDes in TSMC 28nm process node to support wide range of standards like PCI Express, SA...
794
3.0
Multi-Link Multi-Protocol SerDes 10Gbps in TSMC 55LP
Terminus Circuits offers low power, low latency Multistandard SerDes in TSMC 28nm process node to support wide range of standards like PCI Express, SA...
795
3.0
Multi-Link Multi-Protocol SerDes 10Gbps in TSMC 65GP
Terminus Circuits offers low power, low latency Multistandard SerDes in TSMC 28nm process node to support wide range of standards like PCI Express, SA...
796
3.0
Multi-Link Multi-Protocol SerDes 16Gbps in TSMC 28HPC
Terminus Circuits offers low power, low latency Multistandard SerDes in TSMC 28nm process node to support wide range of standards like PCI Express, SA...
797
1.0
2.5V 12Bit pipeline analog to digital converter
TheS65LLV25_ADC_13 IP is a 2.5V 12Bit pipeline analog to digital converter capable of running at up to 100MHz conversion rate with 2Vp-p input range....
798
1.0
S13_DAC_03 CMOS 10-BIT 200MSPS+CURRENT-STEERING D/A Converter
The S13_DAC_03 is a 10-bit resolution, high performance, low power, current-steering CMOS digital-to-analog converter (DAC). The input update rate can...
799
1.0
12-bit 1M Differential Rail to Rail SAR ADC
The analog-to-digital converter uses Successive Approximation Register (SAR) architecture to achieve 12-bit resolution. The ADC includes a core intern...
800
1.0
12-bit 8 Input 1M/200k SAR ADC)
This analog-to-digital converter uses Successive Approximation Register (SAR) architecture to achieve 12-bit resolution. The IP includes a core intern...