Design & Reuse
Catalog of SIP Cores
System on Chip design resources
1958 IP
751
6.0
Camera Demosaicing IP - DAISY (RCCC)
The demosaicing is a color filter interpolation method, and refers to an image processing algorithm for restoring full color values of all pixels in a...
752
6.0
Camera Demosaicing IP - LOTUS (RCCB)
The demosaicing is a color filter interpolation method, and refers to an image processing algorithm for restoring full color values of all pixels in a...
753
6.0
Camera Demosaicing IP - ROSE (RGB-IR)
The demosaicing is a color filter interpolation method, and refers to an image processing algorithm for restoring full color values of all pixels in a...
754
6.0
MIPI D-PHY Receiver with PPI
SP_MIPI_DPHY_RX_PPI _T28HPCP is a MIPI D-PHY Receiver, which complies with MIPI D-PHY specification version 1.2. This D-PHY design receives data from ...
755
6.0
MIPI D-PHY Receiver with PPI
SP_MIPI_DPHY_RX_PPI _T28HPCP is a MIPI D-PHY Receiver, which complies with MIPI D-PHY specification version 1.2. This D-PHY design receives data from ...
756
6.0
MIPI Rx D-PHY
...
757
6.0
LPDDR4/DDR4/DDR3 PHY - TSMC 22nmULL
SP-LPD4/D43_PHY16BIT-T22ULL is designed for DRAM controller to connect to the LPDDR4/DDR4/3 DRAM memory device. It contains a DDR PHY Control Unit(DPC...
758
6.0
USB 2.0 PHY; SMIC 40nm LL
...
759
6.0
USB 2.0 PHY; SMIC 55nm LL
...
760
6.0
USB 3.0 Device
A USB 3.0 Device IP Core that provides high performance SuperSpeed USB connectivity in a small footprint solution for quick and easy implementation of...
761
6.0
LVDS 10 bits dual port transmitter
...
762
5.0
H.264/AVC 1080 60p Baseline Profile Decoder
TMC's TM21745 is a decoder IP core that is compliant with ISO/IEC 14496-10 | ITU-T Rec.H.264. Using TMC's original computer algorithm, we have real...
763
5.0
H.264/AVC 1080 60p Baseline Profile Encoder
- TMC's TM21745 is an encoder IP core that is compliant with ISO/IEC 14496-10 | ITU-T Rec.H.264. - Using TMC's original computer algorithm, we have...
764
5.0
H.264/AVC 4K 60p High Profile Decoder
- TMC's H.264 core (RTL- IP) is designed to be compliant with the H.264 4K Video, which is a highly efficient image compression method standardized in...
765
5.0
H.264/AVC 4K 60p High Profile Encoder
- TMC's H.264 core (RTL- IP) is designed to be compliant with the H.264 4K Video, which is a highly efficient image compression method standardized in...
766
5.0
H.265/HEVC 422 10bit Decoder for 4K
DMNA realizes real time Encoding of 4K (3840 x 2160) and 8K (7680 x 4320) / 60fps video stream compliant with H.265 / HEVC...
767
5.0
H.265/HEVC 422 10bit Encoder for 4K
DMNA realizes real time Encoding of 4K (3840 x 2160) and 8K (7680 x 4320) / 60fps video stream compliant with H.265 / HEVC...
768
5.0
H.265/HEVC H.264/AVC 422 12bit Multi-Codec for 8K
TMC’s HEVC/AVC Multi-Codec IP Core for 4K/8K are designed to be compliant with the H.264 4K (4096 x 2160) Video and H.265 8K (8192 x 4320) Vid...
769
5.0
1:2 Fixed Length Visually Lossless Compression/Decompression
Suppressing the degradation of image quality by the original comp./decomp. processing, drastic reductions of Memory amount and Bandwidth could be real...
770
5.0
1:2 Fixed Length Visually Lossless Compression/Decompression
Suppressing the degradation of image quality by the original comp./decomp. processing, drastic reductions of Memory amount and Bandwidth could be real...
771
5.0
1:3 Fixed Length Visually Lossless Compression/Decompression
Suppressing the degradation of image quality by the original comp./decomp. processing, drastic reductions of Memory amount and Bandwidth could be real...
772
5.0
1:3 Fixed Length Visually Lossless Compression/Decompression
Suppressing the degradation of image quality by the original comp./decomp. processing, drastic reductions of Memory amount and Bandwidth could be real...
773
5.0
1:3 Fixed Length Visually Lossless Compression/Decompression
Suppressing the degradation of image quality by the original comp./decomp. processing, drastic reductions of Memory amount and Bandwidth could be real...
774
5.0
1:4 Fixed Length Visually Lossless Compression/Decompression
Suppressing the degradation of image quality by the original comp./decomp. processing, drastic reductions of Memory amount and Bandwidth could be real...
775
5.0
1:4 Fixed Length Visually Lossless Compression/Decompression
Suppressing the degradation of image quality by the original comp./decomp. processing, drastic reductions of Memory amount and Bandwidth could be real...
776
5.0
1:6 Fixed Length Visually Lossless Compression/Decompression
Suppressing the degradation of image quality by the original comp./decomp. processing, drastic reductions of Memory amount and Bandwidth could be real...
777
5.0
1:6 Fixed Length Visually Lossless Compression/Decompression
Suppressing the degradation of image quality by the original comp./decomp. processing, drastic reductions of Memory amount and Bandwidth could be real...
778
5.0
SAS 4 Port 12G Recorder
The SAS Recorder IP Core provides an ready to use solution for high speed data recording applications. Simple interface guarantees fast time to marke...
779
5.0
SAS Initiator, 12G, 4 Ports, 48 Gbps, SATA Host
The SAS Initiator Controller IP Core provides an interface to high-speed serial link replacement for the parallel SCSI attachment of mass storage devi...
780
5.0
SATA Device IP Core (1.5, 3.0, 6.0 Gbps)
The Serial ATA Device Controller IP Core provides an interface to high-speed serial link replacements for the parallel ATA attachment of mass storage ...
781
5.0
DDI Color Enhancement (CLREN) IP
BTREE's Color Enhancement IP modifies or emphasizes color by controlling Saturation/Luminance/Hue. BTREE's Color Enhancement can only adjust the color...
782
5.0
DDI High Dynamic Range IP
HDR improves the visibility of the output image compared to the input images by increasing the contrast of the image/video reproduced on the display. ...
783
5.0
Serial ATA Host Controller (1.5, 3.0, 6.0 Gb/s)
The Serial ATA Host IP Core provides an interface to high-speed serial link replacements for the parallel ATA attachment of mass storage devices. The ...
784
5.0
Serial ATA Host Controller (1.5, 3.0, 6.0 Gb/s) for Xilinx UltraScale
The Serial ATA Host IP Core provides an interface to high-speed serial link replacements for the parallel ATA attachment of mass storage devices. The ...
785
5.0
Visually LossLess compression hardware RTL core that complies with ISO/IEC-21122-1 (JPEG XS)
TMC’s JPEG XS encoder / decoder IP is Visually LossLess compression / decompression hardware RTL core that complies with ISO/IEC-21122-1 (JPEG XS). T...
786
5.0
Visually LossLess decompression hardware RTL core that complies with ISO/IEC-21122-1 (JPEG XS)
TMC’s JPEG XS encoder / decoder IP is Visually LossLess decompression hardware RTL core that complies with ISO/IEC-21122-1 (JPEG XS). The logic gate ...
787
5.0
Compact LossLess Decoder RTL Core
...
788
5.0
Compact LossLess Encoder RTL Core
...
789
5.0
Lossless / Near lossless Encoder / Decoder Hardware IP
- Lossless / near lossless hardware encoder and decoder IP that features compact and high speed with TMC original algorithm. - Optimized logic gate...
790
5.0
JPEG Decoder 1-pixel/clock
- Baseline JPEG encoder/decoder described in RTL compliant with ISO/IEC 10918-1 - High speed processing with low clock frequency - Suitable for ...
791
5.0
JPEG Encoder 1-pixel/clock
- Baseline JPEG encoder/decoder described in RTL compliant with ISO/IEC 10918-1 - High speed processing with low clock frequency - Suitable for ...
792
5.0
Frame Rate Converter for 4K
TMC’s FRUC (Frame Rate Up-Converter) for 4K RTL Core utilizes proprietary ”DMNA- MEMC” (Motion Estimation and Motion Compensation) algorithm which gen...
793
4.0
DDI Scaler IP - BSCALE
BTREE’s BSCALE enlarges or reduces the input video to fit the panel size. Polynomial Interpolation (PI) is the basic algorithm, and also various metho...
794
4.0
DDI Scaler IP - MSCALE
BTREE’s MSCALE enlarges the input video to fit the panel size. Bi-Linear interpolation is the basic algorithm, and also various methods such as sharpn...
795
4.0
Reed Solomon Decoder IP Core
A high performance, fully configurable Reed Solomon Decoder IP Core that is intended for use in a wide range of applications requiring forward error c...
796
4.0
Reed Solomon Encoder IP Core
A high performance, fully configurable Reed Solomon Encoder IP Core that is intended for use in a wide range of applications requiring forward error c...
797
3.0
High Performance, Low Latency PCIe Gen5 PHY
Terminus Circuits offers best-in-class PHY IP for PCI Express Gen 5/4/3/2/1. The PHY is designed for low latency, low power, small form factor, high i...
798
3.0
High Speed Low Jitter 16GHz Output LC PLL
Terminus Circuits offers an Analog Phase Locked Loop which is a LC oscillator-based integer-N PLL IP powered at 900 mV. The PLL operates with input re...
799
3.0
Single Lane and Quad Lane 10Gbps USB3.1 PHY IP in GF 28SLP process
TERMINUS CIRCUITS USB 3.1 GEN2 PHY is high performance, low power, low latency Single & Quad-Lane PHY that supports USB protocol and its signalling ne...
800
3.0
Single Lane and Quad Lane 10Gbps USB3.1 PHY IP in TSMC 28HPC process
TERMINUS CIRCUITS USB 3.1 GEN2 PHY is high performance, low power, low latency Single & Quad-Lane PHY that supports USB protocol and its signalling ne...