Design & Reuse
1977 IP
1551
0.118
UMC 28nm HPM/HVT Logic and Mixed-Mode Process 7-track Power Slash cell library
UMC 28nm HPM/HVT Logic and Mixed-Mode Process 7-track Power Slash cell library...
1552
0.118
UMC 28nm HPM/LVT Logic and Mixed-Mode Process 7-track ECO_M1 cell library
UMC 28nm HPM/LVT Logic and Mixed-Mode Process 7-track ECO_M1 cell library...
1553
0.118
UMC 28nm HPM/LVT Logic and Mixed-Mode Process 7-track Generic Core cell library
UMC 28nm HPM/LVT Logic and Mixed-Mode Process 7-track Generic Core cell library...
1554
0.118
UMC 28nm HPM/LVT Logic and Mixed-Mode Process 7-track Genernic Core cell library with LMINUS (C31 LVT)
UMC 28nm HPM/LVT Logic and Mixed-Mode Process 7-track Genernic Core cell library with LMINUS (C31 LVT)...
1555
0.118
UMC 28nm HPM/LVT Logic and Mixed-Mode Process 7-track Genernic Core cell library with with LPLUS (C38 LVT)
UMC 28nm HPM/LVT Logic and Mixed-Mode Process 7-track Genernic Core cell library with with LPLUS (C38 LVT)...
1556
0.118
UMC 28nm HPM/LVT Logic and Mixed-Mode Process 7-track Power Slash cell library
UMC 28nm HPM/LVT Logic and Mixed-Mode Process 7-track Power Slash cell library...
1557
0.118
UMC 28nm HPM/RVT Logic and Mixed-Mode Process 12-track generic cell library
UMC 28nm HPM/RVT Logic and Mixed-Mode Process 12-track generic cell library...
1558
0.118
UMC 28nm HPM/RVT Logic and Mixed-Mode Process 12-track generic cell library
UMC 28nm HPM/RVT Logic and Mixed-Mode Process 12-track generic cell library...
1559
0.118
UMC 28nm HPM/RVT Logic and Mixed-Mode Process 12-track powerslash_core library
UMC 28nm HPM/RVT Logic and Mixed-Mode Process 12-track powerslash_core library...
1560
0.118
UMC 28nm HPM/RVT Logic and Mixed-Mode Process 7-track eco_m1 cell library
UMC 28nm HPM/RVT Logic and Mixed-Mode Process 7-track eco_m1 cell library...
1561
0.118
UMC 28nm HPM/RVT Logic and Mixed-Mode Process 7-track generic core cell library
UMC 28nm HPM/RVT Logic and Mixed-Mode Process 7-track generic core cell library...
1562
0.118
UMC 28nm HPM/RVT Logic and Mixed-Mode Process 7-track Genernic Core cell library with LMINUS (C31 RVT)
UMC 28nm HPM/RVT Logic and Mixed-Mode Process 7-track Genernic Core cell library with LMINUS (C31 RVT)...
1563
0.118
UMC 28nm HPM/RVT Logic and Mixed-Mode Process 7-track Genernic Core cell library with with LPLUS (C38 RVT)
UMC 28nm HPM/RVT Logic and Mixed-Mode Process 7-track Genernic Core cell library with with LPLUS (C38 RVT)...
1564
0.118
UMC 28nm HPM/RVT Logic and Mixed-Mode Process 7-track Power Slash cell library
UMC 28nm HPM/RVT Logic and Mixed-Mode Process 7-track Power Slash cell library...
1565
0.118
UMC 28nm Logic and Mixed-Mode HLP/RVT Process, 1.05V Analog ESD IO cell Library
UMC 28nm Logic and Mixed-Mode HLP/RVT Process, 1.05V Analog ESD IO cell Library...
1566
0.118
UMC 28nm Logic and Mixed-Mode HLP/RVT Process, 1.8V Analog ESD IO cell Library
UMC 28nm Logic and Mixed-Mode HLP/RVT Process, 1.8V Analog ESD IO cell Library...
1567
0.118
UMC 28nm Logic and Mixed-Mode HPC Process 3.3V Analog ESD IO cell Library
UMC 28nm Logic and Mixed-Mode HPC Process 3.3V Analog ESD IO cell Library...
1568
0.118
UMC 28nm Logic and Mixed-Mode HPC Process, 1.8V Analog ESD IO cell Library
UMC 28nm Logic and Mixed-Mode HPC Process, 1.8V Analog ESD IO cell Library...
1569
0.118
UMC 28nm Logic and Mixed-Mode HPC Process,0.9V Analog ESD IO cell Library
UMC 28nm Logic and Mixed-Mode HPC Process,0.9V Analog ESD IO cell Library...
1570
0.118
UMC 28nm Logic and Mixed-Mode HPC Processs Multi-Voltage BOAC SD3.0 I/O Cell library
UMC 28nm Logic and Mixed-Mode HPC Processs Multi-Voltage BOAC SD3.0 I/O Cell library...
1571
0.118
UMC 28nm Logic and Mixed-Mode Low-K HPC Process 1.8V BOAC I/O Cell library
UMC 28nm Logic and Mixed-Mode Low-K HPC Process 1.8V BOAC I/O Cell library...
1572
0.118
UMC 28nm Logic and Mixed-Mode Low-K HPC Process True 1.8V High Frequency Oscillator BOAC IO Cell Library
UMC 28nm Logic and Mixed-Mode Low-K HPC Process True 1.8V High Frequency Oscillator BOAC IO Cell Library...
1573
0.118
UMC 28nm Logic and Mixed-Mode Low-K HPC Process True 1.8V Low Power Low Frequency OSC IO Cell Library
UMC 28nm Logic and Mixed-Mode Low-K HPC Process True 1.8V Low Power Low Frequency OSC IO Cell Library...
1574
0.118
UMC 40nm Low Power Process SP-SRAM memory compiler with row redundancy and 213 bit cell
UMC 40nm Low Power Process SP-SRAM memory compiler with row redundancy and 213 bit cell...
1575
0.118
UMC 40nm LP Logic Process Dual-Port SRAM memory compiler with redundancy and LVT peripheral
UMC 40nm LP Logic Process Dual-Port SRAM memory compiler with redundancy and LVT peripheral...
1576
0.118
UMC 55nm Embedded Flash and Embedded E2PROM Low Power Low-K Split-Gate Process Ture 3.3V Generic IO Cell Library
UMC 55nm Embedded Flash and Embedded E2PROM Low Power Low-K Split-Gate Process Ture 3.3V Generic IO Cell Library...
1577
0.118
UMC 55nm Embedded Flash and Embedded E2PROM Low Power Low-K Split-Gate Process Ture 3.3V Low Power Low Frequency OSC IO Cell Library
UMC 55nm Embedded Flash and Embedded E2PROM Low Power Low-K Split-Gate Process Ture 3.3V Low Power Low Frequency OSC IO Cell Library...
1578
0.118
UMC 55nm embedded flash and embedded E2PROM ultra low power split-gate process synchronous well bias feature HVT periphery high density single port SRAM memory compiler with row redundancy.
UMC 55nm embedded flash and embedded E2PROM ultra low power split-gate process synchronous well bias feature HVT periphery high density single port SR...
1579
0.118
UMC 55nm embedded flash and embedded E2PROM ultra low power split-gate process synchronous well bias feature HVT periphery high density single port SRAM memory compiler.
UMC 55nm embedded flash and embedded E2PROM ultra low power split-gate process synchronous well bias feature HVT periphery high density single port SR...
1580
0.118
UMC 55nm embedded flash and embedded E2PROM ultra low power split-gate process synchronous well bias feature HVT+uHVT periphery high density single port SRAM memory compiler with row redundancy.
UMC 55nm embedded flash and embedded E2PROM ultra low power split-gate process synchronous well bias feature HVT+uHVT periphery high density single po...
1581
0.118
UMC 55nm embedded flash and embedded E2PROM ultra low power split-gate process synchronous well bias feature HVT+uHVT periphery high density single port SRAM memory compiler.
UMC 55nm embedded flash and embedded E2PROM ultra low power split-gate process synchronous well bias feature HVT+uHVT periphery high density single po...
1582
0.118
UMC 55nm Embedded Flash and Embedded E2PROM Ultra Low Power Split-Gate Process_x005F_x005F_x005F_x005F_x005F_x000D_
UMC 55nm Embedded Flash and Embedded E2PROM Ultra Low Power Split-Gate Process...
1583
0.118
UMC 55nm embedded flash and embedded e2prom ultra low power split-gate via 1 ROM compiler with well bias
UMC 55nm embedded flash and embedded e2prom ultra low power split-gate via 1 ROM compiler with well bias...
1584
0.118
UMC 55nm embedded flash and embedded e2prom ultra low power splite-gate synchronous via1 rom complier with well bias
UMC 55nm embedded flash and embedded e2prom ultra low power splite-gate synchronous via1 rom complier with well bias...
1585
0.118
UMC 55nm Logic and Mixed-Mode Ultra Low Power / HVT Low-K Process 5V Tolerant BOAC I/O cell library
UMC 55nm Logic and Mixed-Mode Ultra Low Power / HVT Low-K Process 5V Tolerant BOAC I/O cell library...
1586
0.118
UMC 55nm Logic and Mixed-Mode Ultra Low Power Low-K Process 1.8V/2.5V/3.3V multi-voltage BOAC I/O cell library
UMC 55nm Logic and Mixed-Mode Ultra Low Power Low-K Process 1.8V/2.5V/3.3V multi-voltage BOAC I/O cell library...
1587
0.118
UMC 55nm uLP LowK Logic Process One Port Register File with forward biased and UHVT periphery
UMC 55nm uLP LowK Logic Process One Port Register File with forward biased and UHVT periphery...
1588
0.118
UMC 55nm ULP process , Single-Port SRAM with row repair and HVT
UMC 55nm ULP process , Single-Port SRAM with row repair and HVT...
1589
0.118
One Port Register File Compiler IP, Bit-cell: 0.425um2 (HVT), Support retention and deep sleep modes with built-in power gating circuitry., UMC 55nm LP process
UMC 55um LP Low-K process One Port Register File compiler....
1590
0.118
Input 25M~440MHz, output 267M-533M, 200M-400M and 160M-320M, frequency synthesizable PLL; UMC 40nm LP/RVT Logic Process
Input 25M~440MHz, output 267M-533M, 200M-400M and 160M-320M, frequency synthesizable PLL; UMC 40nm LP/RVT Logic Process...
1591
0.118
Input 2MHz~16MHz, output 16~72MHz and 72MHz~200MHz, 1.08~1.32V PLL; UMC 55nm Low Power Process.
Input 2MHz~16MHz, output 16~72MHz and 72MHz~200MHz, 1.08~1.32V PLL; UMC 55nm Low Power Process....
1592
0.118
Input 32.768KHz, Ouput 12 and 24MHz PLL, UMC 0.11um HS/AE (AL Advanced Enhancement) Logic Process
Input 32.768KHz, Ouput 12 and 24MHz PLL, UMC 0.11um HS/AE (AL Advanced Enhancement) Logic Process...
1593
0.118
Input 32.768KHz, Output 12 and 48MHz PLL; UMC 55nm LP/RVT Logic Process
Input 32.768KHz, Output 12 and 48MHz PLL; UMC 55nm LP/RVT Logic Process...
1594
0.118
Input 333M-1600MHz, output 333M-1600MHz, all digital DLL for DDR4 SDRAM controller usage, supports slave delay line to generate 25%/50%/100% delay in period of FREF,UMC 28nm Logic and Mixed-Mode HPC Process.
Input 333M-1600MHz, output 333M-1600MHz, all digital DLL for DDR4 SDRAM controller usage, supports slave delay line to generate 25%/50%/100% delay in ...
1595
0.118
Input 333M-1600MHz, output 333M-1600MHz, all digital slave delay line of FXADDLL340HJ0C to generate 100% delay in period of FREF,UMC 28nm Logic and Mixed-Mode HPC Process
Input 333M-1600MHz, output 333M-1600MHz, all digital slave delay line of FXADDLL340HJ0C to generate 100% delay in period of FREF,UMC 28nm Logic and Mi...
1596
0.118
Input 333M-1600MHz, output 333M-1600MHz, all digital slave delay line of FXADDLL340HJ0C to generate 25% delay in period of FREF,UMC 28nm Logic and Mixed-Mode HPC Process
Input 333M-1600MHz, output 333M-1600MHz, all digital slave delay line of FXADDLL340HJ0C to generate 25% delay in period of FREF,UMC 28nm Logic and Mix...
1597
0.118
Input 333M-1600MHz, output 333M-1600MHz, all digital slave delay line of FXADDLL340HJ0C to generate 50% delay in period of FREF,UMC 28nm Logic and Mixed-Mode HPC Process
Input 333M-1600MHz, output 333M-1600MHz, all digital slave delay line of FXADDLL340HJ0C to generate 50% delay in period of FREF,UMC 28nm Logic and Mix...
1598
0.118
Input 6M-27M Hz, output 10M-850M Hz, frequency synthesizable PLL; UMC 40nm Logic LP RVT and LVT process
Input 6M-27M Hz, output 10M-850M Hz, frequency synthesizable PLL; UMC 40nm Logic LP RVT and LVT process...
1599
0.118
Input 800M-1600MHz, output 800M-1600MHz, all digital slave delay line of FXADDLL340HJ0G to generate 100% delay in period of FREF,UMC 28nm Logic and Mixed-Mode HPM Process
Input 800M-1600MHz, output 800M-1600MHz, all digital slave delay line of FXADDLL340HJ0G to generate 100% delay in period of FREF,UMC 28nm Logic and Mi...
1600
0.118
Input 800M-1600MHz, output 800M-1600MHz, all digital slave delay line of FXADDLL340HJ0G to generate 50% delay in period of FREF,UMC 28nm Logic and Mixed-Mode HPM Process
Input 800M-1600MHz, output 800M-1600MHz, all digital slave delay line of FXADDLL340HJ0G to generate 50% delay in period of FREF,UMC 28nm Logic and Mix...