Design & Reuse
598 IP
201
14.0
Tensilica HiFi 5 DSP
AI and DSP performance leader with up to 4X the NN performance and 2X the DSP performance of the HiFi 4 DSP, ideal for digital a Blending a neural ne...
202
14.0
Tensilica Vision P1 DSP
The latest addition to the Vision DSP family, built using 128-bit SIMD and offering up to 0.4TOPs of performance The Cadence® Tensilica® Vision P1 DS...
203
14.0
Tensilica Vision P6 DSP
First DSP for embedded vision and AI with millions of units shipped in the market The Cadence® Tensilica® Vision P6 DSP, introduced in 2016, sets a n...
204
14.0
Tensilica Vision Q7 DSP
Built on our latest Xtensa NX architecture and offers up to 2.18TOPS of performance The Cadence® Tensilica® Vision Q7 DSP delivers up to 2.18 tera op...
205
14.0
Tensilica Vision Q8 DSP
Built using 1024-bit SIMD and offering up to 3.84TOPS of performance The Cadence® Tensilica® Vision Q8 DSP delivers up to 3.84 tera operations per se...
206
14.0
Tensilica Xtensa LX Processor Platform
Versatile 32-bit RISC processor with configurable 5/7-stage pipeline addressing a wide range of application requirements ranging The Cadence® Tensili...
207
14.0
Tensilica Xtensa NX Processor Platform
32-bit RISC processor with 10-stage pipeline offers performance of over 2GHz suitable for embedded applications with high perfor The Cadence® Tensili...
208
14.0
1G to 200G High Speed Channelized Ethernet Controller MAC/PCS/FEC
200G aggregate bandwidth channelized solution for up to four Ethernet channels Cadence High Speed Ethernet Controller IP supports multi-channel Ether...
209
14.0
MIPI CSI-2 RX Controller for v2.1
CSI-2 receiver controller for application processor The Cadence® Receiver (RX) Controller IP for MIPI® Camera Serial Interface 2 (CSI-2SM) is respons...
210
14.0
MIPI CSI-2 TX Controller for v2.1
CSI-2 transmitter controller for application processor The Cadence® Transmitter (TX) Controller IP for MIPI DSI is compliant with the MIPI® Alliance ...
211
14.0
MIPI D-PHY for TSMC
D-PHY physical layer Developed by experienced teams with industry-leading domain expertise and extensively validated by multiple hardware platforms, ...
212
14.0
MIPI DSI TX Controller
DSI transmitter controller for application The Cadence® Transmitter (TX) Controller IP for MIPI DSI is compliant with the MIPI® Alliance Specificatio...
213
14.0
UltraLink Controller
Ultralink controller for high performance die-to-die interconnect on streaming, CXS, and AXI protocols The Cadence Ultralink Controller enables a pro...
214
14.0
Universal Chiplet Interconnect Express (UCIe 1.0) Controller
Ultra-low latency UCIe controller for standard industry chiplet interoperability on streaming, PCIe, and CXL protocols The Cadence UCIe™ Controller i...
215
14.0
Universal Chiplet Interconnect Express (UCIe 1.0) Controller
Ultra-low latency UCIe controller for standard industry chiplet interoperability on streaming, PCIe, and CXL protocols The Cadence UCIe™ Controller i...
216
14.0
Controller for MIPI Soundwire
Audio data transport The Cadence® IP Family for MIPI® Protocols delivers area-optimized interface IP with the low power and high performance required...
217
14.0
USB 2.0 Controller
Mature controller solution for OTG and Device applications Certified for compliance with Universal Serial Bus Specification, Revision 2.0, the Cadenc...
218
14.0
USB 2.0 PHY for TSMC
Proven PHY IP for USB Device, Host, and OTG with small footprint and low active power The ubiquity of USB 2.0 in devices makes it nearly mandatory fo...
219
14.0
USB 3.0 xHCI Host Controller
Mature solutions featuring xHCI Host, Device, and Dual-Role Device Compliant with Universal Serial Bus 3.0 Specification, Revision 1.0 and xHCI Speci...
220
14.0
USB 3.1 Device Controller
Mature solutions featuring xHCI Host, Device, and Dual-Role Certified for compliance with USB 3.1 Specification v1.0, and xHCI Specification v1.0, th...
221
14.0
USXGMII Ethernet PCS (PCSR_X)
The Cadence USXGMII PCS (PCSR_X) IP provides the logic required to integrate a USXGMII, 5GBASE-R, or 10GBASE-R PCS into any system on chip (SoC). The...
222
14.0
Ethernet XAUI PCS
Integrates MAC IP to a broad range of PHY and SerDes IP The Cadence Ethernet XAUI Physical Coding Sublayer (PCS) IP provides the logic required to in...
223
14.0
Dual-Role Device Controller for USB 3.0
Mature solutions featuring xHCI Host, Device, and Dual-Role Certified for compliance with USB 3.0 Specification v1.0, and xHCI Specification v1.0, th...
224
14.0
Dual-Role Device Controller for USB 3.1
Mature solutions featuring xHCI Host, Device, and Dual-Role Certified for compliance with USB 3.1 Specification v1.0, and xHCI Specification v1.0, th...
225
14.0
CXL Controller
Low-latency Controller IP for cache-coherent root-port, end-point, and dual-mode applications The Cadence® Controller IP for CXL provides the logic r...
226
10.0
D-phy 1.2 on tsmc 22nm with ultra low power
Arasan Chip Systems announces the immediate availability its MIPI D-PHY IP supporting speeds of upto 2.5 gbps for TSMC 22nm SoC designs. The MIPI D-...
227
10.0
I3C Device Controller v1.2
The Arasan I3C Device Controller IP Implements Device Controller functionality as defined by the MIPI Alliance’s I3C Specification. The I3C bus is us...
228
10.0
I3C Dual Controller v1.2
The Arasan I3C Secondary Controller IP Core implements Active controller functionality as defined by the MIPI Alliance’s I3C Specification and Seconda...
229
10.0
I3C Slave Controller
The Arasan I3C Slave Controller IP Core Implements Slave functionality as defined by the MIPI Alliance’s I3C Specification. The I3C bus is used for va...
230
10.0
SD 3.0 / SDIO 3.0 Combo Device Controller
The SD / SDIO 3.0 Combo Device IP Core is a high performance controller capable of interfacing with memory cards and I/O applications such as WLAN, Bl...
231
10.0
SD 4.0 Device Controller
The SD 4.0 Device IP core is used to implement SD cards connected to a Host processor over standard SD bus. The flexible architecture of SD Device IP ...
232
10.0
SD 4.1 SDIO 4.1 Host Controller IP
The SD 4.1/SDIO 4.1 IP from Arasan Chip Systems is a highly integrated host controller IP solution that supports two key memory card I/O technologies:...
233
10.0
SDIO 3.0 Device Controller
Arasan's SDIO 3.0 Device IP is used to implement high-performance SDIO cards that connect to a Host processor over a standard SD bus. The SDIO 3.0 Dev...
234
10.0
MIPI D-PHY TSMC 130nm
Arasan delivers you a MIPI D-PHY in the process node and lane configuration you need, conforming to your specific design constraints, with a complete ...
235
10.0
MIPI D-PHY TSMC 28nm HPC+ @ 2.5Ghz
The Arasan’s MIPI D-PHY Analog Transceiver IP Core is fully compliant to the D-PHY specification version 1.1. It supports the MIPI® Camera Serial Inte...
236
10.0
MIPI DSI-2 Transmit Controller v1.0
The Arasan DSI-2 Device Controller IP is designed to provide MIPI DSI-2 1.0 compliant high speed serial connectivity for mobile host processors using ...
237
10.0
MIPI I3C PHY I/O
Arasan’s MIPI I3CⓇ PHY I/O IP, in compliance with MIPI I3CⓇ specifications v1.1. Arasan’s MIPI I3CⓇ PHY IP is part of Arasan’s Total IP Solution for M...
238
10.0
MIPI M-PHY Designed For TSMC 28nm
ACS-AIP-MPHY-28HPM MIPI Specification Version 3.0 is a low pin count, power efficient, inter-chip serial interface with high bandwidth capabilities. A...
239
10.0
MIPI M-PHY G4 Designed For TSMC 28nm HPC+
ACS-AIP-MPHY-28HPC+ MIPI Specification Version 4.1 is a low pin count, power efficient, inter-chip serial interface with high bandwidth capabilities. ...
240
10.0
eMMC 4.51 Device Controller
Arasan's eMMC 4.51 Memory controller is compliant with the latest MMC 4.51 specification released by JEDEC. The controller provides a peak bandwidth o...
241
10.0
eMMC 5.1 HS400 PHY and I/O Pads in TSMC 16FF PLUS LL
Arasan provides a HS400 compatible PHY that customers can integrate with the HS400 I/O PADs. It is designed to optimize I/O performance with a core v...
242
10.0
eMMC 5.1 HS400 PHY and I/O Pads in TSMC 16FFC NS
Arasan provides a HS400 compatible PHY that customers can integrate with the HS400 I/O PADs. It is designed to optimize I/O performance with a core v...
243
10.0
eMMC 5.1 HS400 PHY and I/O Pads in TSMC 28 HPC-EW
Arasan provides a HS400 compatible PHY that customers can integrate with the HS400 I/O PADs. It is designed to optimize I/O performance with a core v...
244
10.0
eMMC 5.1 HS400 PHY and I/O Pads in TSMC 28HPC PLUS
Arasan provides a HS400 compatible PHY that customers can integrate with the HS400 I/O PADs. It is designed to optimize I/O performance with a core v...
245
10.0
eMMC 5.1 HS400 PHY and I/O Pads in TSMC 40LP-EW
Arasan provides a HS400 compatible PHY that customers can integrate with the HS400 I/O PADs. It is designed to optimize I/O performance with a core v...
246
10.0
ONFI 3.2 NAND Flash Controller
The Arasan ONFI 3.2 compliant NAND Flash Controller IP Core is a full featured, easy to use, synthesizable design that is easily integrated into any S...
247
10.0
Complete suite of development tools, ARC development systems and operating systems for embedded software application development
Synopsys offers a complete suite of development tools, ARC development systems and operating systems, providing everything a developer needs to effici...
248
7.0
10 Bit 40 MS/s Pipeline ADC
The IP consists of a 10 bit 40 MS/s pipeline ADC. A time-interleaved architecture with 1.5 bit per stage is used. The operational amplifiers are share...
249
7.0
12 Bit 17 kS/s Cyclic ADC
This cyclic ADC, based on redundant-signed-digit (RSD) conversion, is optimized for power efficiency and high accuracy. It provides 12 bit resolution ...
250
7.0
12 Bit 20 MS/s Pipeline ADC
This pipelined ADC can be applied for up to 20MSps sampling frequencies. By using interleaved switched-capacitor circuitries a CLK signal with half ...