Design and Reuse exits IP catalog standards program
![]() |
Design and Reuse exits IP catalog standards program
By Peter Clarke, EE Times
March 20, 2000 (2:59 p.m. EST)
URL: http://www.eetimes.com/story/OEG20000317S0004
LONDON Design and Reuse SA has pulled out of a collaborative effort to develop standards for the secure transfer of virtual component information over the Internet, and from a pilot program to test those standards. The decision comes days before demonstrations of the work at the Design Automation and Test Europe (Date) conference, scheduled to start March 27 in Paris. The collaboration, overseen by the Silicon Integration Initiative (SI2), includes database infrastructure provider Synchronicity Inc. (Marlboro, Mass.), the Virtual Component Exchange (VCX), the IP developers' industry organization Rapid, and Nokia Research Center (Bochum, Germany). The effort focused on the use of XML to "tag" intellectual property (IP) core descriptions. Tagging lets a single query search multiple Internet catalogs of cores on key parameters in a controlled way, according to the collaborators. Last November the pilot program participants, including Design and Reuse (Grenoble, France), agreed to develop standards and tools based on the Virtual Component Transfer specifications of the Virtual Socket Interface Alliance, SI2's Electronic Component Information Exchange QuickData specifications, and the VCX business and legal tools and services. Design and Reuse (D&R) has now moved away from the plan to use a common XML-based front end, which could reduce the significance of back-end differences in IP catalogs. Future plans "D&R has decided to withdraw from the SI2 XML initiative . . . we think that it was really too biased toward Synchronicity and VCX," said D&R chairwoman Gabriele Saucier. "We will copyright our own IPML language for IP exchange," Saucier said. Saucier said she felt the standards, and the way they we re presented, would encourage people to visit VCX's Web site as a first port of call, and to use Synchronicity's catalog infrastructure software. Therefore, it was not in D&R's commercial interest. CMP Media Inc., publisher of EE Times, owns a 19 percent share of D&R. Don Cottrell, vice president of technology at SI2, said, "[D&R's departure] doesn't affect the pilot program. It just means we have one less database to work with." Mark Miller, vice president of business development at Synchronicity, said, "I can't imagine why D&R would not want to be part of something with this much momentum. It's already up and running, and we'll be giving the first demonstrations at the Date conference in Paris. "There's no grand scheme here," Miller added. "It just so happens that Synchronicity has provided the infrastructure for a lot of the IP catalogs being developed around the world, including those of VCX, Rapid and Synopsys' IP Catalyst. All we did was implement and effectively execute a protocol d efined by SI2." D&R's Saucier said, "We don't want designers to be able to meta-search in our database without making a contract with us. So we are working on our own IPML, an XML tag implementation dedicated to IP. We expect it to be complete within one month and should be able to demonstrate it at DAC," which will take place June 5-9 in Los Angeles.
Related News
- IC Manage GDP-XL Enterprise IP Catalog enables NXP to Improve IP Asset Management and Reuse
- Thalia's IP reuse platform joins Cadence Connections EDA Program
- IEEE Standards Association and Via Licensing Corporation Collaborate to Foster Intellectual Property Licensing Programs for IEEE Standards
- DAC panelists call for IP reuse standards
- Bluespec Joins The SPIRIT Consortium to Advance IP Reuse Interoperability Standards for SoC Design
Breaking News
- Arteris Joins Intel Foundry Accelerator Ecosystem Alliance Program to Support Advanced Semiconductor Designs
- SkyeChip Joins Intel Foundry Accelerator IP Alliance
- Siemens and Intel Foundry advance their collaboration to enable cutting-edge integrated circuits and advanced packaging solutions for 2D and 3D IC
- Cadence Expands Design IP Portfolio Optimized for Intel 18A and Intel 18A-P Technologies, Advancing AI, HPC and Mobility Applications
- Synopsys and Intel Foundry Propel Angstrom-Scale Chip Designs on Intel 18A and Intel 18A-P Technologies
Most Popular
- QuickLogic Delivers eFPGA Hard IP for Intel 18A Based Test Chip
- Siemens collaborates with TSMC to drive further innovation in semiconductor design and integration
- Aion Silicon Joins Intel Foundry Accelerator Design Services Alliance to Deliver Next-Generation Custom SoCs at Scale
- TSMC Unveils Next-Generation A14 Process at North America Technology Symposium
- BOS Semiconductors to Partner with Intel to Accelerate Automotive AI Innovation
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |