Increasing popularity of AI applications and DPU architecture has led to growing demand for higher SRAM densities, in turn placing challenges on SRAM yield and reliability.
www.embedded.com/, Jul. 15, 2024 –
Along with the rise of the internet of things (IoT), mobile devices, and edge computing, the boom in AI-enhanced features has enabled the addition of even greater functionality in applications such as intelligent sensing, in-vehicle driver assistance (ADAS), and voice recognition, all of which require the use of increasingly larger training models.
However, as the progress of CPU performance slows, new ideas to reduce the I/O and data loading on CPUs are becoming more popular. These include such solutions as DPU or PIM (process in memory) architectures, as well as the introduction of hierarchical data processing. However, as more CPUs are required for hierarchical processing, there is a corresponding need for more SRAM caches to serve these high-speed CPUs. Thus, the increasing popularity of AI applications and DPU architecture implementations has led to growing demand for higher SRAM densities.
Challenges to SRAM yield and reliability
SRAM is a major driving force behind the advancement of CMOS technology, and with the rise of AI applications, the amount of on-chip SRAM is expected to soar from tens to hundreds of MB. In principle, the higher the density of the SRAM, the higher the chances of producing bad cells, a non-trivial threat to wafer yields. In addition, there are other challenges to solve during the development of a new process technology:
One is that photolithography and etching technologies are no longer able to advance in accordance with Moore's Law as previously seen, even for the latest FinFET technologies. As a result, transistor sizes and metal pitches cannot be reduced as much, so that each successive generation of SRAM memory cells may not be shrunk as much as before.
The second is that as feature sizes shrink and transistor density increases, the power consumed by the transistors leads to an even higher rise in die temperature. This in turn causes the static leakage current of the transistors to rise, resulting in a decrease in the SRAM static noise margin (SNM).
Due to the above challenges to SRAM yield and reliability, the ability to repair SRAMs has become very important.