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• Chips&Media Launches Cframe60: A Lossless & Lossy frame Compression Standalone HW IP (Thursday, August 21, 2025)
• Arteris Wins Gold Stevie® Award for Most Innovative Tech Company of the Year (Tuesday, August 19, 2025)
• MIPI C/D PHY and DSI Controller IP Licensed by Tier-1 US Customer, Strengthening T2M's Position in Automotive and AR/VR Markets (Monday, August 18, 2025)
• CFX's 40nm HV Process OTP IP Now Available at Fab (Monday, August 18, 2025)
• Brite Semiconductor Releases PCIe 4.0 PHY IP (Thursday, August 14, 2025)
• Perceptia Completes Silicon Characterisation of pPLL03 for GF 22FDX - Report Now Available (Thursday, August 14, 2025)
• CFX Achieves Major Breakthrough in 40nm SONOS Embedded eFlash IP (Thursday, August 7, 2025)
• ALi Corporation and Ceva Announce Strategic Collaboration to Bring Scalable Edge AI to Next-Gen Video Platforms (Thursday, August 7, 2025)
• Arasan Announces the industries first MIPI SWI3S Manager IP and Peripheral Controller IP (Thursday, August 7, 2025)
• BrainChip launches Akida Cloud for instant access to latest Akida neuromorphic technology (Wednesday, August 6, 2025)
• PCI-SIG® Announces PCI Express® 8.0 Specification to Reach 256.0 GT/s (Tuesday, August 5, 2025)
• Codasip looks to Silicon Creations' PLL to drive RISC-V Automotive Safety-Critical Core (Tuesday, August 5, 2025)
• UCIe Consortium Introduces 3.0 Specification With 64 GT/s Performance and Enhanced Manageability (Tuesday, August 5, 2025)
• Advanced GNSS IP Cores (RF + Digital + Software) for Enhanced Positioning, Navigation, & Tracking for Next-Gen Products (Monday, August 4, 2025)
• Creonic Releases DVB-S2X Demodulator Version 6.0 with Increased Bitwidth and Annex M Support (Thursday, July 31, 2025)
• Perceptia Releases Design Kit for pPLL05 on GlobalFoundries 22FDX Platform (Thursday, July 31, 2025)
• Next-Gen High-Speed Transceiver IP Core Unveiled: Power, Performance, and Protocol Versatility in One Core (Monday, July 28, 2025)
• Mixel Supports Automotive SerDes Alliance (ASA) Motion Link SerDes IP (Wednesday, July 23, 2025)
• Arteris Selected by Whalechip for Near-Memory Computing Chip (Tuesday, July 22, 2025)
• EnSilica cuts post-quantum cryptography (PQC) silicon area with three-in-one IP block (Monday, July 21, 2025)
• 12-bit 5Msps High-Speed, Silicon-Proven ADC IP Core Available for Immediate Licensing (Monday, July 21, 2025)
• Cadence Races First to Release LPDDR6/5X Memory IP for AI Infrastructure (Friday, July 18, 2025)
• Perceptia Devices Release pPLL08W, best-in-class RF PLL IP in GF22FDX (Thursday, July 17, 2025)
• Innosilicon Scales LPDDR5X/5/4X/4 and DDR5/4 Combo IPs to 28nm and 22nm, Cementing Its Position as the "One Stop" for Memory Interface Solutions (Thursday, July 17, 2025)
• InPsytech Tapes Out F2F SoIC Design Compliant with UCIE 2.0 Standard Enabling High-Speed Interconnects for 3D Heterogeneous Integration (Wednesday, July 16, 2025)
• GUC Tapes Out Industry-Leading UCIe Face-Up IP for TSMC SoIC-X (Tuesday, July 15, 2025)
• JEDEC Releases New LPDDR6 Standard to Enhance Mobile and AI Memory Performance (Friday, July 11, 2025)
• Arasan Announces immediate availability of its Total IP for Embedded USB2 (eUSB2) with Controller and PHY (Friday, July 11, 2025)
• Cadence Introduces Industry-First LPDDR6/5X 14.4Gbps Memory IP to Power Next-Generation AI Infrastructure (Wednesday, July 9, 2025)
• Custom ASIC Design for CGM, TPMS & SATCOM applications from T2M-IP (Wednesday, July 9, 2025)
• PUFsecurity, a subsidiary of eMemory, Achieves NIST CAVP Certification for PQC Algorithms, Launches PUFpqc Architecture for Quantum-Resilient SoCs (Tuesday, July 8, 2025)
• Ethernet IP Core for Next-Gen Automotive SoCs: Complementing CAN, LIN, and FlexRay with Scalable Connectivity (Monday, June 30, 2025)
• CAST Releases First Dual LZ4 and Snappy Lossless Data Compression IP Core (Friday, June 27, 2025)
• FH (Frequency Hopping) - OFDM Modem Available For Immediate Implementation From Global IP Core (Friday, June 27, 2025)
• VeriSilicon Expands DSP Portfolio with Silicon-Proven ZSP5000 Vision Core Series for Edge Intelligence (Thursday, June 26, 2025)
• eMemory's NeoFuse OTP Qualifies on TSMC's N3P Process, Enabling Secure Memory for Advanced AI and HPC Chips (Thursday, June 26, 2025)
• Sofics Delivers Remarkable PPA & R Performance Near Physical Limits on TSMC 2nm Technology (Wednesday, June 25, 2025)
• AMD will launch PCIe 6.0 devices next year but consumers will have to wait almost half a decade to get it - here's why (Tuesday, June 24, 2025)
• Ceva Launches MotionEngine™ Hex: Bringing Precise, Touch-Free, Spatial Control to Smart TV, Gaming, and IoT Interfaces (Tuesday, June 24, 2025)
• Creonic's DVB-S2 and DVB-S2X IP Cores Now Support the New DVB-NIP Standard (Tuesday, June 24, 2025)
• Faraday Delivers Latest SerDes IP to Complete Interface Lineup on UMC's 22nm Platform (Tuesday, June 24, 2025)
• SignatureIP Unveils Industry-Leading CXL 3.2 Solution for High-Performance Computing (Monday, June 23, 2025)
• Arteris Addresses Silicon Design Reuse Challenge with New Magillem Packaging Product for IP Blocks and Chiplets (Monday, June 23, 2025)
• Certified Automotive Ethernet, CAN XL, and LIN IP Cores — Proven, Qualified, and Ready for Seamless Integration (Monday, June 23, 2025)
• True Circuits Announces New and Improved Low-jitter Digital Ultra+ PLL that Offers Exceptional Performance, Features and Ease of Use (Monday, June 23, 2025)
• True Circuits Introduces the Low-jitter Digital Ultra+ PLL at the Design Automation Conference (Friday, June 20, 2025)
• CAST Launches Multi-Channel DMA IP Core Ideal for Streaming Applications (Thursday, June 19, 2025)
• DCD-SEMI Joins MIPI Alliance and Unveils Latest I3C IP at MIPI Plugfest Warsaw 2025 (Wednesday, June 18, 2025)
• Arteris Accelerates AI-Driven Silicon Innovation with Expanded Multi-Die Solution (Tuesday, June 17, 2025)
• SmartDV Introduces Advanced H.264 and H.265 Video Encoder and Decoder IP (Monday, June 16, 2025)