www.eetimes.com, Jul. 26, 2024 –
A recent standard update by the JEDEC Solid State Technology Association is enhancing the security and reliability of DDR5 SDRAM, while Rambus has added power management capabilities to DDR5 DIMMs.
Security and power management at the memory-device level has become increasingly important with the growth of AI workloads as models and proprietary algorithms represent highly valuable IP and AI-driven data centers threaten to drive up power consumption.
The JESD79-5C DDR5 SDRAM standard introduces per-row activation counting (PRAC) to improve DRAM data integrity to enhance performance in a wide range of applications, from high-performance servers to emerging technologies like AI and machine learning, as well as improve security. PRAC precisely counts DRAM activations on a worldline granularity, so when the DRAM detects an excessive number of activations, it alerts the system to pause traffic and to designate time for mitigative measures.
In a briefing with EE Times, JEDEC JC-42 committee chair Christopher Cox said the standards reflect how security is a fundamental cornerstone of DRAM design, whether it is DDR, LPDDR, GDDR or HBM. "We have to keep it secure."
But threats are constantly evolving, so as soon as vulnerabilities are discovered they must be addressed in the appropriate memory standard, he said. "As you can imagine with silicon, it takes a little bit longer to do that."
Cox said security is table stakes along with power and performance requirements. With DDR5, there were additional mitigations for security threats like RowHammer as part of an effort to harden DRAM against vulnerabilities. PRAC functionality is an extension of those capabilities, which is adding counters on every single row inside of the DRAM–there can be thousands of rows, he said. "Now we have micro counters for every one of these rows, so we can watch for misbehaving activity where somebody's trying to activate that device too much and it's outside of just normal read access."