Meeting the challenge of larger, more complex SoCs to address todays ever-increasing computing demands.
newelectronics.co.uk, Oct. 17, 2024 –
Modern system-on-chip (SoC) design architectures are evolving rapidly, driven by a variety of factors. Traditional SoC design methodology partitions key design components into proprietary, differentiated accelerators or cores alongside reusable, standards-based IP components and subsystems. Until recently, SoC designs were implemented as monolithic designs with all design elements - both proprietary and licensed- integrated into a single piece of silicon. Today, this monolithic approach is evolving to a more disaggregated, or 'sum of chiplets', approach.
This evolution is facilitated by several developments that have helped address the challenges of increasingly complex SoCs. Monolithic silicon approaches now often bump up against silicon manufacturing reticle limits, outstripping the capabilities of Moore's Law scaling. In addition, advanced-node silicon takes far longer to reach mature yields and requires longer design cycles. Not only are wafer manufacturing cycles getting longer, but intrinsic silicon wafer costs are increasing and the rising cost per transistor (CPT) has begun to outweigh the benefits of technology scaling that historically have come with advancements in process technology. Today's SoC designers must be far more judicious in deciding which design elements to move to the next node and which to maintain in older nodes to achieve a more scalable cost and development framework.
The rise of chiplets
To address these challenges, designers now employ multi-die strategies, using chiplets, to develop large system SoCs. This involves disaggregating the SoC into smaller subsystem die serving different functions, which are matched to the most appropriate process node. Breaking an SoC into separate components helps to solve the issues of design complexity, design cycle times, die size, yield and time to market.
The semiconductor ecosystem, including foundries, EDA companies, SoC providers, and assembly and packaging companies, has begun exploring chiplet designs due to the decreasing silicon economies of scale. Many semiconductor manufacturers have discovered that chiplets make building systems faster and cheaper than monolithic or even prior multi-die solutions.
When properly architected, chiplets provide greater product flexibility, allowing teams to focus on their unique value-add while reducing risk and minimising costs. The chiplet value proposition is akin to silicon IP, which is now ubiquitous in today's SoC designs.
Chiplets allow SoC providers to leverage design partners for advanced-node designs. Designers can develop entire product roadmaps built around a library of chiplets, resulting in better portfolio management. Complex IP integration can be achieved faster with outright reuse, outsourcing, or minor modifications to an existing chiplet without completely modifying an entire design. There are also important verification and post-silicon advantages to chiplets and disaggregated designs that go beyond just manufacturing realisation. Designers can leverage the extensive software partner ecosystem through reference designs and utilise off-the-shelf chiplets to build products.