Electronic design firm Synopsys announced Wednesday it has expanded its strategic partnership with TSMC, enabling optimized design work on its latest A16 and N2P processes.
www.taiwannews.com.tw/en, May. 14, 2025 –
A16 is TSMC’s latest process defined at 1.6 nm whereas N2P refers to 2 nm. Generally, the smaller the process, the more advanced the chip.
Synopsys said in a press release that its certified design flows now support both nodes, improving design quality and speeding up analogue migration, per CNA. Certified backside routing capabilities will further enhance power delivery and chip performance.
It also announced the integration of its Synopsys.ai platform within the certified flows for A16 and N2P, boosting productivity. Work has already begun on EDA flows for TSMC’s future A14 node.
The company is also advancing 3D integration with its 3DIC Compiler, now certified for TSMC’s chip-on-water-on-substrate (CoWoS) technology and 3Dblox, delivering a 5.5x increase in interposer size.
TSMC Senior Director Yuan Li-pen (袁立本) said the close collaboration ensures customers can access certified tools to meet aggressive design goals. Accelerating time-to-market through high-quality SoC designs is at the heart of our long-standing partnership with Synopsys, he added.