Codasip: Toward Custom, Safe, Secure RISC-V Compute Cores

May. 19, 2025, May. 19, 2025 – 

Emmanuel Till-Vattier, VP of Sales EMEA at Codasip, presented a brief product update at this week’s RISC-V Summit Europe 2025 in Paris.

By Anne-Françoise Pelé, EETimes Europe (May 15, 2025) 

In a keynote speech at the RISC-V Summit Europe 2025 in Paris, Emmanuel Till-Vattier, VP of sales EMEA at Codasip, presented a brief product update, including new possibilities for fast migration from Arm to RISC-V, new core customization features, and the latest advances in Capability Hardware Enhanced RISC Instructions (CHERI) memory protection.

Codasip focuses on three goals, Till-Vattier said: “One is making RISC-V cores easy to customize. Two is making them safe. And three is security.”

In early May, the Munich-based company launched Codasip L150, a “low-power, area-efficient, three-stage, 32-bit RISC-V core” designed for real-time embedded applications.

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