eenewseurope.com, May. 14, 2025 –
Flow Computing in Finland has started alpha testing of a RISC-V compiler for its Parallel Processing Unit (PPU) AI block.
The PPU is capable of increasing any CPU architecture by up to 100X by using the compiler enables source code to take advantage of the architecture. The first target compilations have shown that the loops common in RISC-V CPU models can be significantly reduced by recompiling the existing code, reaching the 100X expected performance.
This compares to a 2x improvement without recompilation by simply replacing some CPU cores with PPUs with no change to the source code.
The compiler identifies parallel elements in the existing source code that can be effectively sped up by the PPU. Code is analysed to identify what parts can be enhanced by PPU acceleration and then the compiler then assigns parallelizable functionality directly to the PPU, bypassing CPU bottlenecks.
“What we have amply demonstrated in this early development phase is that simple parallel workloads cause massive loops in CPUs without PPU enhancement – whereas in CPUs with PPUs, those loops are significantly reduced (if not practically eliminated),” said Dr. Martti Forsell, CTO, Chief Architect and co-founder of Flow Computing, a spinout of Finnish research lab VTT.