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RISC-V News

• EU DARE Project Is Scrambling to Replace Codasip (Monday, April 27, 2026)
• Wind River Joins the CHERI Alliance and Collaborates with Innovate UK to Accelerate Cybersecurity Innovation (Thursday, April 23, 2026)
• RISC-V SoC supports voice-enabled IoT devices (Monday, April 13, 2026)
• SiFive Raises $400 Million to Accelerate High-Performance RISC-V Data Center Solutions; Company Valuation Now Stands at $3.65 Billion (Monday, April 13, 2026)
• Samsung Takes First Step Away From ARM’s Ecosystem By Working On An SSD Controller Chip Based On RISC-V Architecture (Thursday, April 9, 2026)
• Codasip announces strategic pivot and divestiture (Wednesday, April 8, 2026)
• China’s tech self-sufficiency drive reaches new milestone with powerful RISC-V chips (Monday, April 6, 2026)
• Samsung Readies PCIe 5.0 QLC SSD with a Custom RISC-V Controller (Thursday, April 2, 2026)
• Switzerland is at the centre of a quiet rebellion in chip design (Monday, March 30, 2026)
• Alibaba delivers RISC-V server chip optimized to run China’s top AI models (Thursday, March 26, 2026)
• Reliable performance with RISC-V: Why architecture, microarchitecture and compilers must work together (Thursday, March 26, 2026)
• TDE000S – Secure, Compact RISC-V IP Core Processing (Tuesday, March 24, 2026)
• MIPS and Green Hills Software Accelerate Safety Certified Product Development for MIPS RISC-V Microcontrollers (Thursday, March 19, 2026)
• Tenstorrent QuietBox 2 Brings RISC‑V AI Inference to the Desktop (Thursday, March 19, 2026)
• RISC-V TDS350N IP Core: A55-Class Performance, AI Acceleration processor for AI and ML Scenarios (Friday, March 13, 2026)
• Samsung to Make Ubitium’s Universal RISC-V Processor (Thursday, March 12, 2026)
• The path to RISC-V growth: Why software consistency is becoming crucial (Monday, March 9, 2026)
• The Rise of RISC-V (Thursday, March 5, 2026)
• RISC-V IP Core, Powering Next-Gen Automotive & AI SoCs (Tuesday, March 3, 2026)
• RISC-V IP Core - TAE520 : R52, Comparable Performance functional-safety processor (Monday, February 23, 2026)
• RISC-V Pivots from Academia to Industrial Heavyweight (Monday, February 16, 2026)
• RISC-V IP Core Portfolio at Embedded World 2026, Powering Next-Gen Embedded Systems for Automotive, IoT & Industrial Systems… (Monday, February 16, 2026)
• RISC-V IP Core: T2M to Present Production-Proven RISC-V IP Core at Mobile World Congress, 2026 (Monday, February 9, 2026)
• Fabless Startup Aheesa Tapes Out First Indian RISC-V Network SoC (Monday, February 9, 2026)
• Phison Selects Andes RISC-V Cores for its First aiDAPTIV+ AI Solution, Marking a Major Milestone in AI Architecture (Monday, February 9, 2026)
• Andes Technology Launches RISC-V Now! — A Global Conference Series Focused on Commercial, Production-Scale RISC-V (Tuesday, February 3, 2026)
• MIPS accelerates the development timeline of the RISC-V NPU S8200, integrating Synopsys ARC IP to transform into a "physical AI" computing platform. (Monday, February 2, 2026)
• TGE302 RISC-V IP Core: M0+, Comparable Performance Low-Power General-Purpose Processor (Monday, February 2, 2026)
• The OpenHW Foundation unveils the first industry-ready RISC-V ecosystem to advance European digital sovereignty (Thursday, January 29, 2026)
• MIPS Takes ‘Software-First Approach’ With New RISC-V NPUs (Thursday, January 29, 2026)
• Nuclei Announces Strategic Global Expansion to Accelerate RISC-V Adoption in 2026 (Wednesday, January 28, 2026)
• SiFive to Power Next-Gen RISC-V AI Data Centers with NVIDIA NVLink Fusion (Monday, January 19, 2026)
• LTSCT and Andes Technology Sign Strategic IP Licensing Master Agreement to accelerate RISC-V Based Advanced Semiconductor Solutions (Tuesday, January 13, 2026)
• 6 Snapshots Show RISC-V Solidifying Its Stronghold in Products and Plans (Monday, January 12, 2026)
• T2M Presents TGE100 RISC-V CPU Core: Ultra-Low-Power Computing for Area-Constrained IoT and MCU Platforms (Monday, January 12, 2026)
• Quintauris and SiFive Announce Partnership to Advance RISC-V Ecosystem Development (Monday, January 12, 2026)
• Quintauris Demonstrates RISC-V Innovation in Automotive at CES (Monday, January 12, 2026)
• Meta and Qualcomm push RISC-V market share towards 25% (Thursday, January 8, 2026)
• Arm sheds billions in market capitalization after Qualcomm hints at RISC-V adoption with Ventara Micro acquisition (Monday, December 22, 2025)
• India Launches DHRUV64, First Indigenous 64-Bit Dual-Core Processor (Friday, December 19, 2025)
• VeriSilicon responds to the termination of the acquisition of Nuclei Smart Fusion: The RISC-V business layout plan remains unchanged, and the Point Semiconductor merger is proceeding concurrently. (Thursday, December 18, 2025)
• India Unveils DHRUV64: Nation’s First Indigenous 64-Bit Dual-Core Microprocessor (Thursday, December 18, 2025)
• SiFive and IAR Collaborate to Advance the Automotive Ecosystem and Drive RISC-V Innovation in Automotive Electronics (Thursday, December 18, 2025)
• ISOLDE Project Demonstrates Advancements in European Open-Source RISC-V for Automotive, Space, and IoT (Monday, December 15, 2025)
• Quintauris and SiFive Announce Partnership to Advance RISC-V Ecosystem Development (Monday, December 15, 2025)
• Qualcomm Acquires Ventana Micro Systems, Deepening RISC-V CPU Expertise (Thursday, December 11, 2025)
• India Paves Dual RISC-V Tracks with C-DAC and Startup Silicon (Thursday, December 11, 2025)
• Tenstorrent Blackhole Support & Other New RISC-V + ARM64 Hardware In Linux 6.19 (Thursday, December 11, 2025)
• Risc-v Cores and Neuromorphic Arrays Enable Scalable Digital Processors for EdgeAI Applications (Monday, December 8, 2025)
• Tenstorrent QuietBox tested: A high-performance RISC-V AI workstation trapped in a software blackhole (Thursday, November 27, 2025)