With nanosecond resolution of transistor-level voltages, the on-chip power delivery network analyzer provides new insights to optimize SoC performance.
www.allaboutcircuits.com, May. 20, 2025 –
Movellus recently announced a new on-chip sensor that detects power transients on a nanosecond scale. The new IP provides transistor-level power delivery analytics that may improve the design and debug process at every step of fabrication.
Power delivery networks (PDNs) are an extremely important component of any electrical system, ranging from industrial power distribution to chip-level designs. In many cases, however, it is not possible or reasonable to accurately monitor the dynamic behavior of voltages at every point in the system. This is doubly true for densely integrated chips, making Movellus’ new IP an innovation with the potential to greatly impact the development of SoCs and ASICs.
At the heart of almost every electronic system is the PDN, responsible for routing power from a source or regulator to the necessary components. For an industrial design, this could consist of transformers and DC-DC converters, while on a PCB, this could take the form of board-level capacitors and traces. In these designs, it is relatively trivial to identify static and transient errors since the traces carrying the power are readily accessible.
On-chip, however, is another story. In the case of fabricated silicon, it is not always possible to directly probe the transistor-level voltages that can drastically impact circuit performance. In the case of SoCs or high-power processors, the transistor-level voltages can have a major impact on the efficiency and performance of the resulting chip. Currently, it is possible to model these dynamics, but intra- and inter-wafer process variations can still not be easily accounted for. As a result, a robust and efficient on-chip power analysis solution could be a useful tool for designers.
Movellus is taking a process-agnostic approach with its PDN IQ, which can be integrated into several different processes for maximum flexibility. Each PDN IQ can provide up to nanosecond resolution, making even the fastest transients on GHz-clock chips readily accessible.
On-chip, however, is another story. In the case of fabricated silicon, it is not always possible to directly probe the transistor-level voltages that can drastically impact circuit performance. In the case of SoCs or high-power processors, the transistor-level voltages can have a major impact on the efficiency and performance of the resulting chip. Currently, it is possible to model these dynamics, but intra- and inter-wafer process variations can still not be easily accounted for. As a result, a robust and efficient on-chip power analysis solution could be a useful tool for designers.
Movellus is taking a process-agnostic approach with its PDN IQ, which can be integrated into several different processes for maximum flexibility. Each PDN IQ can provide up to nanosecond resolution, making even the fastest transients on GHz-clock chips readily accessible.
This bit of Movellus IP provides considerable new insights into the dynamic operation of SoCs, and allows designers to make more informed decisions at every step in the fabrication process. In characterization, the PDN IQ optimizes the chips’ performance levels while simultaneously providing a new route to evaluating performance during testing or heterogeneous integration. Finally, in the field, designers can use the PDN IQ to analyze each unique workload and determine the best voltage level for maximum performance.
Movellus claims the PDN IQ can provide more insight into the effects of heterogeneous integration. If, for example, multiple chiplets with a PDN IQ block are interconnected, the additional analytics would give designers a remarkably deeper understanding of their device’s performance. This not only enables better development but could also open the doors for all new heterogeneous integration approaches that were previously not possible.