It's been a year of change so far for the RISC-V movement, from new leadership to an outpouring of hardware.
www.allaboutcircuits.com, May. 21, 2025 –
In fifteen years, RISC-V has gone from an academic project at UC Berkeley to one of the major technological trends in compute. The ISA has since flourished in an era that appreciates its royalty-free, open-source building blocks.
In recent weeks, RISC-V has celebrated several notable wins, from major organizational announcements to new RISC-V-based technologies hitting the market.
In honor of RISC-V’s recent 15-year anniversary, SiFive published a brief history and optimistic forecast on the future of the ISA.
In 2010, RISC-V was born from the Parallel Computing Laboratory (Par Lab) at UC Berkeley. At the time, the ISA presented a new approach that avoided legacy instruction complexity to achieve modular scalability. Over time, the architecture’s open nature drove broad adoption, now present in billions of devices and backed by more than 4,500 members in 70 countries.
SiFive itself was founded by RISC-V’s creators and has translated this architecture into commercially viable IP cores ranging from minimal embedded controllers to high-performance vector processors. To date, its technology stack has shipped in over two billion devices and includes proprietary contributions like WorldGuard and vector-matrix extensions.
As proprietary ISAs raise concerns over vendor lock-in, SiFive anticipates that industry leaders will increasingly rely on RISC-V to decouple hardware design from legacy constraints and to enable full-stack hardware customization.
RISC-V International, the leading organization driving the RISC-V movement, recently underwent a leadership shift, appointing Andrea Gallo as its new CEO.
The RISC-V board selected Gallo based on his technical fluency and track record of driving multilateral collaboration in open computing environments. Before his appointment as CEO, Gallo previously served as vice president of technology at RISC-V and held leadership roles at Linaro and STMicroelectronics, where he focused on open-source development and cross-industry collaboration.
Now, as CEO of RISC-V International, Gallo intends to scale technical and educational resource access, establish a formal RISC-V certification program, and increase member engagement across sectors and geographies. He also plans to expand coordination with the RISC-V Software Ecosystem (RISE) initiative to improve developer tooling and streamline integration across platforms.
SiFive and Kinara recently introduced a USB-based development module that provides bare-metal access to the SiFive X280 RISC-V vector processor.
The HiFive Xara X280 integrates Kinara’s Ara-2 SoC, which includes dual 64-bit SiFive X280 cores and support for real-time vector processing, floating-point computation, and tensor operations. In this module, the X280 cores interface directly with Kinara’s neural processing units, delivering up to 40 TOPS, and support transformer-based models such as LLaVA and LLaMA.