The pressure to move data faster due to AI growth is reflected in the latest iteration of the PCIe. PCIe 7.0 is now officially available, and the update is targeting data-driven applications like AI/machine learning, 800G Ethernet, cloud and quantum computing.
www.eetimes.com, Jun. 18, 2025 –
Among the specification’s key features are a 128.0 GT/s raw bit rate and up to 512 GB/s bi-directionally via x16 configuration, signaling that uses Pulse Amplitude Modulation with 4 levels (PAM4) and Flitbased encoding, and improved power efficiency.
“It’s an evolutionary approach because we already have PAM4 that we introduced in 6.0,” PCI-SIG president Al Yanes said in a briefing, adding that Flitbased encoding was also introduced in the previous update.
As with all updates to the PCIe specification, 7.0 maintains backwards compatibility with previous generations of PCIe technology, as well as the long-standing tradition of doubling the I/O bandwidth every three years, according to Yanes.
“It takes three years to develop a specification. It takes three years for innovation. It takes three years for feedback on the previous technology,” he said. “This is our sweet spot.”
Yanes added that it is not easy to double clock rates, which is why tape-out and validation takes three years.
The primary impetus for the improvements in PCIe 7.0 is to help meet the bandwidth demands of data-intensive markets deploying AI, including hyperscale data centers and high-performance computing. In addition, the latest iteration also supports the needs of military/aerospace and automotive use cases, Yanes said.
The PCI-SIG has been eyeing automotive since 2022 since the release of 6.0. “We’ve been trying to give a wider adoption there. We’re hoping that the need for performance will push [automotive] closer to PCI express.”
In addition to the PCIe 7.0 update, the PCI-SIG also announced the introduction of the industry’s first standard-based Optical Aware Retimer solution. Yanes said the organization’s optical working group has been able to standardize optical PCIe architecture in a way that is easily transferred to existing PCIe 6.0 designs and devices and is included in the new PCIe 7.0 specification. Working group members includes experts from the domains of logic, protocol, optical and electrical.
Aimed at AI, cloud and data center environments, the Optical Aware Retimer Engineering Change Notice amends the PCIe 6.4 specification and the new PCIe 7.0 specification to include a PCIe retimer-based solution, providing the first standardized way to implement PCIe technology over optical fiber.
The Optical Aware Retimer enables various optical technologies for optical interconnection between existing PCIe 6.4 and 7.0 compliant switch, root-complex and endpoint silicon designs, as well as extended reach across racks and pods. The retimer also allows multiplexing and data mapping across electrical and optical domains—all while enabling more compact implementations than electrical copper solutions.
Aside from updates to the specification itself, Yanes also highlighted that the PCI-SIG organization that defines PCIe reached 1,000 members in November 2024. It was originally formed in 1992, with PCIe 1.0 released in 2003.
Even though 7.0 is now available with a handful of companies doing demo products, compliance testing for 6.0 is still in progress so that members can test their products, Yanes said, with the aim to establish an integrators list by the end of the year. “You have to nurse it along if you want successful wide adoption.”
In the meantime, pathfinding for the PCIe 8.0 specification is already in progress, Yanes said. “The journey doesn’t stop here. If you’re not pedaling, you’re going down the hill.”