Jun. 23, 2025 –
Los Altos, California, June 23, 2025 -- True Circuits, Inc. (TCI), a leading provider of analog and mixed-signal intellectual property (IP) for the semiconductor, systems and electronics industries announced today the availability of a new and improved low-jitter digital LC PLL that is well suited for the most demanding chip applications, including high-speed SerDes and ADC input clocks. The “Ultra+ PLL” is designed as an ultra-low jitter, extremely wide range clock multiplier with precise fractional frequency control and optional spread spectrum capability, giving chip designers the ultimate in performance, features and ease of use. True Circuits has added a state-of-the-art digital control algorithm to this flagship PLL in collaboration with Stanford VLSI group using carefully guided, but conventional place-and-route technology. With this technology added to TCI’s arsenal of high-productivity tools, the new flow opens the door for an expansion of our product portfolio, and for customers to add their own features. The new digital control loop cuts the lock time by as much as 70%, while directly controlling the loop bandwidth accurately and consistently across PVT. The Ultra+ PLL will be available in TSMC processes from 28nm to 5nm.
A new control algorithm
The innovative digital control algorithm used in the Ultra+ PLL achieves unprecedented loop bandwidth precision, enabling user-defined settings as accurate as 0.1% of Fref – with further accuracy scaling available on demand. Critically, this precise bandwidth is maintained consistently across PVT variations through continuous background loop-gain calibration. This eliminates performance drift, ensuring stable PLL dynamics (lock time, jitter tolerance) without manual intervention under any operating condition. Integrated correlated noise and spurious measurement circuits provide active immunity against environmental disturbances. By continuously monitoring and analyzing correlated noise components, the PLL guarantees stable operation even in excessively noisy environments. This built-in intelligence distinguishes external threats from intrinsic noise, delivering unmatched resilience for mission-critical clocking applications.
Adding to a first of its kind, the Ultra PLL
The original Ultra PLL is the most sophisticated PLL in the world and employs a state-of-the-art architecture and uses high-speed digital and analog circuits to achieve exceptional performance, with many useful features. It has been in production for over eight years in a variety of high-performance products. It is highly programmable so one PLL can be used for all applications on a SoC. Using a high-Q, LC oscillator, it has low jitter performance (<500fs) for the most demanding SerDes and ADC reference clocks and ultra-wide multiplication range (1-250,000) to support reference clocks from 32KHz to 1GHz. The PLL also offers precise frequency control with a least 26 fractional bits (at least 10 precise) for extremely high fractional-N resolution. It can generate precise and adjustable frequency spreading with programmable rate and depth to meet tight FCC requirements.
Compared to the competition, the Ultra PLL is 1/5 the size, lower power and has many one-of-a-kind features referenced above. By adapting the internal division ratio to match the LC VCO's natural frequency, the new control loop used in the Ultra+ PLL enables wide output frequency coverage without demanding a large tuning range LC tank. This allows the use of a compact, very high-Q LC tank, which results in a significant improvement in jitter performance (<100fs) over the original design, while maintaining its small size, low-power and programmability.
Building on TCI’s unique development flow
The new control logic was created using conventional, digital place and route. This approach adds to True Circuits’ JSPICE™ Design Environment (JDE™) development flow that already uses unique analog and high-speed digital cells that are placed algorithmically, while maintaining the control needed for critical circuits.
Using carefully controlled conventional tools along with JDE, TCI will build an expanded portfolio of feature-rich, synthesizable PLLs and DLLs. In addition, customers can be provided synthesizable or hardened IP with a modular design so that they can build their own features easily and safely using hard macros and stock Verilog code.
“The growing complexity of today’s SoCs and FPGAs presents chip designers with ever increasing challenges that often result in compromises on features, performance and flexibility”, remarked Brian Gardner, True Circuits’ V.P. of Business Development. “Our goal is to help chip designers tackle these challenges with a single digital PLL that offers broad functionality and performance in an easy to use programmable design. The improvements we have made to the already world-class Ultra PLL show our commitment to technological innovation. Whether the need is ultra-low jitter for a SerDes, precise frequency resolution for HDMI or extremely low phase noise for an ADC, our new Ultra+ PLL has them covered.”
Price and Availability
True Circuits Ultra+ PLLs will be available in TSMC processes from 28nm to 5nm. Front-end views will be ready for delivery in the month of September, with tapeout ready GDSII to follow shortly thereafter. Customers can license TCI timing IP either directly from TCI or through its global network of design services partners and sales reps. The hard macros are available for a per use license fee and no royalty fees. The license fee includes integration support from TCI and its partners to ensure a successful customer tape out. The deliverables include GDSII and LVS Spice netlists, behavioral and synthesis models, Library Exchange Format (LEF) files and extensive user documentation.
About True Circuits Analog PLLs and DLLs
True Circuits offers a complete family of standardized and silicon-proven general purpose, clock generator, deskew, spread spectrum, IoT and Ultra PLLs, and multi-slave and multi-phase DLLs that spans nearly all performance points and features typically requested by ASIC, FPGA and SoC designers. These high quality, low-jitter PLL and DLL hard macros are suited to a wide variety of interface standards and chip applications. They are pin-programmable, highly process tolerant and reusable. They are also easy to integrate and are fully supported, so customers can reduce both design and silicon risks.
True Circuits PLLs support a wide range of frequencies, multiplication factors and functions over which they deliver optimal performance, avoiding the cost and complexity of licensing multiple point-solution PLLs or fiddling with digital PLLs. TCI’s PLLs are available with ring-oscillator and LC-tank architectures, fractional-N division and frequency spreading for EMI reduction. TCI's DLLs are available in multi-slave and multi-phase versions and different sizes and form factors. They delay a set of signals by precise and adjustable fractions of a reference clock cycle independent of voltage and temperature and are ideal for high-speed DDR and ONFI interface applications. Customized PLL and DLL solutions are also available for specialized chip applications.
True Circuits PLLs and DLLs are available for immediate customer delivery in TSMC, GLOBALFOUNDRIES and UMC processes from 180nm to 5nm. For more information about True Circuits IP products, visit www.truecircuits.com/tci_technology.html and www.truecircuits.com/product_matrix.html.
About True Circuits Synthesizable PLLs and DLLs
The synthesizable Precision PLL generates multiple precision clocks supporting any modulation scheme from almost DC to 10GHz. The outputs can be independently dynamically programmed cycle-by-cycle to any clock period and the clock frequency can be a precise ratio of floating point numbers times the reference frequency. The integrated phase noise is better than 500ps RMS. It is ideal for SerDes, processor and DVFS applications.
The synthesizable micro PLL is a small synthesizable general-purpose PLL that multiplies the reference clock by any integer or fractional-N value from 1 to 500K. It supports reference clock frequencies as low as 32KHz and output frequencies as high as 3GHz. It can stay locked to the reference clock while it changes over a 10:1 frequency range. Because it is synthesizable, it can support spreading as well as other modulation profiles. It is relatively low power, very fast locking and can quickly restart from a sleep mode.
The synthesizable micro DLL is a small synthesizable DLL with a master and multiple slaves topology. It can support reference frequencies typically in the range of 500MHz to 3GHz and track reference changes over an 8:1 frequency range while providing 9-bit accuracy in slave delay programming. Slave delays can be changed glitch free and the DLL can quickly restart from a sleep mode. It has a very small zero code offset that can be precisely cancelled.
About True Circuits DDR PHYs
The DDR PHY is a high-performance, scalable system using a radically new architecture that continuously and automatically adjusts each pin individually, correcting skew within byte lanes. This state-of-the-art tuning acts independently on each pin, data phase and chip select value. Read gate and data eye timing are also continuously adjusted. Fully automatic training is managed by a light weight special purpose processor and includes multi-cycle write leveling and read gate training and also read/write data eye training, including PHY Vref and DRAM Vref settings.
The PHY employs a localized and optimized PHY-to-memory controller interface to ease timing closure. The circuitry in each pin is able to measure the data eye and jitter, and calculate flight delays. The PHY also includes a full speed read/write BIST, which tests the complete read and write paths of every pin simultaneously with pseudo-random data.
Remarkable physical flexibility allows the PHY to adapt to each customer's die floorplan and package constraints, yet is verified and delivered as a unit for easy timing closure with no assembly required. The PHY supports LPDDR5, DDR4, LPDDR4, DDR3 and LPDDR3, and is DFI 5.1 compliant. When combined with an appropriate DDR memory controller, a complete and fully-automatic DDR system is realized.
The True Circuits DDR PHY is silicon proven and available for customer delivery in a variety of TSMC processes from 40nm to 5nm. Interested customers can obtain more product information on the web at www.truecircuits.com/ddr_phy.html or by contacting True Circuits at sales@truecircuits.com.
About JDE™
JDE is a powerful design environment developed and used by True Circuits over the last 27years to create complex analog and digital circuits from 250nm to 5nm. It is a tightly integrated collection of tools and capabilities that greatly simplifies and expedites the process of designing and characterizing circuits in a standardized, centralized and repeatable way. JDE enables users to run massively parallel simulations, either locally or in the cloud, or both with unlimited JSPICE™ simulator licenses. JDE includes a measurement and data analysis environment that is packed with functions and reduces massive data into insightful information that builds intuition and encourages exploration. JDE incorporates text, processing code and scripts that move analog design into the realm of modern software. JDE moves layout from mostly hand-drawn to cell-based without losing the layout control needed for critical circuits.
For more information about JDE, visit www.truecircuits.com/jspice.html.
About True Circuits
True Circuits develops and markets a broad range of industry leading PLLs, DLLs and DDR PHY hard macros for ICs for the semiconductor, systems and electronics industries. TCI's robust state-of-the-art circuits, methodical and proven design strategy, and close association with the world's leading foundries, IDMs, and design services companies allow the company to quickly and reliably create new and innovative designs in a variety of advanced process technologies. Over the last 27 years, True Circuits has distinguished itself as the technology leader in the timing IP space, and its PLLs and DLLs are used extensively around the world in its customers' products with production volumes well into the billions.
True Circuits is headquartered at 4300 El Camino Real, Suite 200, Los Altos, California 94022 and can be found on the web at www.truecircuits.com. Product inquiries can be made by calling the company directly at (650) 949-3400 or via e-mail at sales@truecircuits.com.