A team of researchers from the Institute of Science Tokyo (Science Tokyo), Japan, has conceptualised an innovative 2.5D/3D chip integration approach called BBCube.
www.eenewsembedded.com, Jun. 23, 2025 –
Traditional system-in-package (SiP) approaches, where semiconductor chips are arranged in a two-dimensional plane (2D) using solder bumps, have size-related limitations, warranting the development of novel chip integration technologies. For high-performance computing, the researchers developed a novel power supply technology by employing a 3D stacked computing architecture, which consists of processing units placed directly above stacks of dynamic random-access memory, marking a significant advance in 3D chip packaging.
To implement BBCube, the researchers developed key technologies involving precise and high-speed bonding techniques and adhesive technology. These new technologies can help address the demands of high-performance computing applications, which require both high memory bandwidth and low power consumption, with reduced power supply noise.
The research team, comprising Professors Norio Chujo and Takayuki Ohba, along with other scientists from the Institute of Integrated Research’s WOW Alliance Heterogeneous and Functional Integration Unit at the Institute of Science Tokyo (Science Tokyo), Japan, initially developed a face-down chip-on-wafer (COW) process to circumvent the limitations of using solder interconnects. Utilising inkjet technology and a selective adhesive coating method, they successfully carried out sequential bonding of different chip sizes onto a 300 mm waffle wafer with a narrow chip-to-chip spacing of 10 μm and a minimal mount loading time of less than 10 milliseconds. Explaining the precise COW process, Chujo comments, “More than 30,000 chips of various sizes were fabricated onto the waffle wafer, achieving enhanced bonding speed without any chip-detachment failures.
To enable this precise and high-speed COW process, the researchers focused on addressing thermal stability issues that can affect the multilevel stacking of ultra-thin wafers. By carefully designing the chemical properties, they developed a novel adhesive material, called ‘DPAS300,’ that can be used in both COW and wafer-on-wafer processes. This new adhesive, composed of an organic–inorganic hybrid structure, exhibited appreciable adhesiveness and heat resistance during experimental studies.
Finally, to achieve high memory bandwidth and improve the power integrity of BBCube, the scientists employed a 3D xPU-on-DRAM architecture reinforced by a new power distribution highway. This included embedding capacitors between xPU and DRAM, implementing redistribution layers on the waffle wafer, and placing through-silicon vias in wafer lanes and DRAM scribe lines. “These innovations reduced the energy required for data transmission to one-fifth to one-twentieth of that in conventional systems, while also suppressing power supply noise to below 50 mV,” states Chujo, highlighting the benefits of 3D stacked computing architecture.
Taken together, the 3D chip integration technologies developed by researchers from Science Tokyo have the potential to transform next-generation computing architectures.
Image: BBCube™ — Bumpless Build Cube. A bumpless three-dimensional semiconductor integrating technology can address the challenges posed by traditional SiP approaches. Credit: Institute of Science Tokyo.