The world we are living in is increasingly becoming software-defined, where artificial intelligence (AI) is adding the next layer of functionality. And it's driving the need for more compute to enable the software-enabled functionality. However, with this huge progression in compute content, Moore's Law scaling will be insufficient to support the number of transistors for the needed compute.
www.edn.com, Jun. 24, 2025 –
Enter 3D ICs, disaggregating the functionality of silicon into a set of chiplets and then heterogeneously integrating them on an advanced integration platform. “Hyperscalers, driving the compute envelope, are particularly pushing the extreme where 3D ICs are needed,” said Michael White, VP of Calibre Design Solutions at Siemens EDA.
White also noted automotive designs where self-driving technology content is driving the need for 3D ICs. At the Design Automation Conference (DAC) held in San Francisco, California, on 22-25 June 2025, Siemens EDA announced two key additions to its EDA portfolio to address and overcome the complexity challenges associated with the design and manufacture of 2.5D and 3D IC devices.
First, the company’s Innovator3D IC suite enables chip designers to efficiently author, simulate, and manage heterogeneously integrated 2.5D and 3D IC designs. Second, its Calibre 3DStress software leverages advanced thermo-mechanical analysis to identify the electrical impact of stress at the transistor level.