The upgraded multi-die IP solution may speed the SoC design process in an AI-driven market that demands greater chip performance.
www.allaboutcircuits.com, Jul. 02, 2025 –
Arteris recently announced the expansion of its multi-die IP solution. The new upgrades to the company’s network-on-chip (NoC) IP library include the FlexNoC Network-on-Chip with CodaCache Last-Level Cache, the Arteris Ncore Configurable Coherent Interconnect, and the Magillem Connectivity design software.
Arteris says these two new IP solutions and design software will improve key SoC development workflows with automation. The upgraded capability can enable high-performance, multi-die chip designs in less time and improve scalability without redesign. Arteris' NoC IP implements high-speed, chiplet-to-chiplet communications within the highest performing multi-die design topologies.
To catch up to the demands of AI and modern computing technology, developers and tool providers are increasingly relying on multi-die chiplet designs. Spreading functional blocks out to independent chiplets has a number of advantages over monolithic designs.
For one, building with proven IP blocks and proven interconnect IP technology cab reduce SoC design cycle times. Chiplets also allow specialists to design subsections, so a company that, for example, focuses on processing cores does not need to specialize in memory or IO.
Monolithic chips require a greater area of silicon. A wafer defect in any part of the chip area is likely to lead to the rejection of the entire chip. In contrast, a chiplet wafer will isolate such a defect, leading to the loss of only one chiplet, delivering greater wafer yields. Breaking a large chip into chiplets and utilizing high-performance NoC IP improves the routing of power, ground, and data paths between functional areas of the SoC.
Multi-die architecture comes in two primary topologies: homogeneous scale-out and heterogeneous disaggregation. A homogeneous scale-out is typically used for SoCs with multiple chiplets of the same type—such as multiple processing cores or an array of memory chiplets. Arteris FlexNoC and Ncore are designed to allow significant scaling within the same basic design.