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• Mirabilis Design Signs OEM Agreement with Cadence to Deliver VisualSim for System-Level Modeling and Performance Optimization (Monday, June 23, 2025)
• Siemens turbocharges semiconductor and PCB design portfolio with generative and agentic AI (Monday, June 23, 2025)
• Keysight Enables AMD to Showcase Electrical PCI Express® Compliance up to 64 GT/s (Thursday, June 19, 2025)
• Siemens collaborates with Samsung Foundry on advanced node product certifications and EDA innovation (Wednesday, June 18, 2025)
• Cadence Accelerates SoC, 3D-IC and Chiplet Design for AI Data Centers, Automotive and Connectivity in Collaboration with Samsung Foundry (Tuesday, June 17, 2025)
• Synopsys Accelerates AI and Multi-Die Design Innovation on Advanced Samsung Foundry Processes (Tuesday, June 17, 2025)
• InCore Unveils SoC Generator Platform: From Idea to FPGA Validation in Minutes; Demonstrates Silicon Proof of Auto-Generated SoC (Monday, June 16, 2025)
• Imec achieves record-breaking RF GaN-on-Si transistor performance for high-efficiency 6G power amplifiers (Thursday, June 12, 2025)
• Cadence Advances Design and Engineering for Europe's Manufacturers on NVIDIA Industrial AI Cloud (Wednesday, June 11, 2025)
• OPENEDGES Collaborates with Renesas on Memory Subsystem IPs for Next-Generation MPU Platform Development (Wednesday, June 11, 2025)
• Siemens' PAVE360 to support new Arm Zena Compute Subsystems (Wednesday, June 11, 2025)
• Keysight and Synopsys Deliver an AI-Powered RF Design Migration Flow for Transition from TSMC's N6RF+ to N4P Process Node (Friday, June 6, 2025)
• Plug and Play Expands Semiconductor Ecosystem Program with New Synopsys Collaboration to Accelerate Chip Design Innovation (Thursday, June 5, 2025)
• Using Design-to-Test Workflows and Managing the IP Lifecycle in Chiplet Designs (Wednesday, June 4, 2025)
• Siemens and IBM collaborate to bring SysML v2 model-based systems engineering to Siemens Xcelerator (Monday, June 2, 2025)
• AI memory chip guru to unveil road map for next-generation HBMs (Thursday, May 29, 2025)
• Arteris Bridges Hardware-Software Gap with New EDA Tool (Wednesday, May 28, 2025)
• Siemens to bring advanced timing constraint capabilities to EDA design flow with Excellicon acquisition (Monday, May 19, 2025)
• Perforce Partners with Siemens for Software-Defined, AI-Powered, Silicon-Enabled Design (Friday, May 16, 2025)
• Siemens leverages AI to close industry's IC verification productivity gap in new Questa One smart verification solution (Wednesday, May 14, 2025)
• Alps Alpine Adopts Silvaco's Jivaro Pro to Accelerate SPICE Post-Layout Simulation (Tuesday, May 13, 2025)
• PQSecure Partners with Menta SAS to Demonstrate Leakage-Resistant PQC IPs on eFPGA Fabric (Friday, May 9, 2025)
• Cybord's Visual AI solution to be integrated with Siemens' Opcenter MES (Wednesday, May 7, 2025)
• Excelliance MOS Adopts Silvaco DTCO Flow for the Development of Next-Gen Silicon Carbide Devices (Tuesday, May 6, 2025)
• CELUS Design Platform integrates with Cadence's OrCAD X Platform (Tuesday, May 6, 2025)
• Thalia enhances AMALIA Platform with new AI models to revolutionize analog, RF and mixed-signal IC design migration (Thursday, May 1, 2025)
• Movellus Debuts Industry-First On-Die Power Delivery Network Analyzer (Thursday, May 1, 2025)
• Imec coordinates EU Chips Design Platform (Wednesday, April 30, 2025)
• Thalia enhances AMALIA Platform with new AI models to revolutionize analog, RF and mixed-signal IC (Tuesday, April 29, 2025)
• NEXT Semiconductor Technologies Collaborates with BAE Systems to Develop Next Generation Space-Qualified Chips (Monday, April 28, 2025)
• Faraday Adds QuickLogic eFPGA to FlashKit‑22RRAM SoC for IoT Edge (Friday, April 25, 2025)
• Thalia joins GlobalFoundries' GlobalSolutions Ecosystem to advance IP reuse and design migration (Tuesday, April 22, 2025)
• MosChip® to showcase Silicon Engineering Services at TSMC 2025 North America Technology Symposium (Tuesday, April 22, 2025)
• Automating Hardware-Software Consistency in Complex SoCs (Monday, April 21, 2025)
• Secafy selects Siemens' EDA tools for innovative hardware security development (Wednesday, April 16, 2025)
• Orthogone Technologies and Blackcore® Technologies Announce Strategic Partnership to Deliver Ultra-Low Latency Solutions for High-Frequency Trading (Wednesday, April 16, 2025)
• Why Do Hyperscalers Design Their Own CPUs? (Monday, April 14, 2025)
• Semiwise Completes the Development of the Virtual Reality Semiconductor Fabrication Training Facility (Wednesday, April 9, 2025)
• Semiwise Completes the Development of the Virtual Reality Semiconductor Fabrication Training Facility (Tuesday, April 8, 2025)
• HCLTech joins Samsung Advanced Foundry Ecosystem as a Design Solution Partner (Thursday, April 3, 2025)
• ProMOS Adopts Silvaco Victory TCAD Solution for the Development of Next-Gen Silicon Photonics Devices (Tuesday, April 1, 2025)
• Exploring the Rationale for HAV in Complex SoCs (Monday, March 31, 2025)
• Movellus and RTX's SEAKR Engineering Collaborate on Advancing Mission-Critical ASICs (Monday, March 31, 2025)
• X-FAB, SMART Photonics and Epiphany Design demonstrate InP-on-Silicon design flow for next-generation optical transceivers at OFC (Sunday, March 30, 2025)
• PolarFire® SoC FPGAs Achieve AEC-Q100 Qualification (Tuesday, March 25, 2025)
• Siemens acquires Altair to create most complete AI-powered portfolio of industrial software (Tuesday, March 25, 2025)
• Cadence Launches Conformal AI Studio, Improves SoC Productivity by 10x (Tuesday, March 25, 2025)
• Strategies for Addressing More Complex Custom Chip Design (Sunday, March 23, 2025)
• EnSilica Agrees a Multimillion Pound Design and Manufacturing Services Contract (Sunday, March 23, 2025)
• 'World-Leading' Semiconductor Design Centre Will 'Strengthen Wales' Leadership in Chip Design' (Sunday, March 23, 2025)