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• Synopsys Introduces Digital Twin Racetrack and NVIDIA Omniverse to STEM Racing (Monday, September 29, 2025)
• The Quantum Race: Finding Europe's Formula 1 (Thursday, September 25, 2025)
• Synopsys Collaborates with TSMC to Drive the Next Wave of AI and Multi-Die Innovation (Thursday, September 25, 2025)
• Siemens collaborates with TSMC to accelerate 3D IC and AI-driven circuit and systems design (Thursday, September 25, 2025)
• Cadence Partners with TSMC to Power Next-Generation Innovations Using AI Flows and IP for TSMC Advanced Nodes and 3DFabric (Thursday, September 25, 2025)
• Siemens adds AI to Simcenter Testlab to reinvent modal testing and analysis processes (Wednesday, September 24, 2025)
• Thalia and X-FAB Forge Strategic Partnership to Safeguard Supply and Accelerate IP Migration (Tuesday, September 23, 2025)
• Siemens accelerates complex semiconductor design and test with Tessent IJTAG Pro (Tuesday, September 23, 2025)
• Analog Power Conversion LLC adopts Silvaco’s Design Technology Co-Optimization Flow for Next Generation Silicon and Silicon Carbide Power Devices (Tuesday, September 16, 2025)
• Siemens unveils groundbreaking Tessent AnalogTest software for automated analog circuit test generation (Tuesday, September 16, 2025)
• Arm Goes for Rebrand for Mobile CSS, Drops Cortex, Immortalis (Monday, September 15, 2025)
• Perforce's Delphix AI used in software development to boost speed and security (Wednesday, September 10, 2025)
• Cadence Expands Digital Twin Platform Library with NVIDIA DGX SuperPOD Model to Accelerate AI Data Center Deployment and Operations (Wednesday, September 10, 2025)
• Synopsys and GlobalFoundries Establish Pilot Program to Bring Chip Design and Manufacturing to University Classrooms (Monday, September 8, 2025)
• Data Patterns (India) Ltd. connects design to manufacturing with software from Siemens Xcelerator (Thursday, September 4, 2025)
• Synopsys Announces Expanding AI Capabilities for its Leading EDA Solutions (Thursday, September 4, 2025)
• The 3 Hidden Risks That Can Derail Your IC Design Project! How to Avoid Them? (Tuesday, September 2, 2025)
• How Synopsys De-Risks The Road From Concept To Chip (Tuesday, August 26, 2025)
• MSU Leveraging Intel 16 and the Cadence Tool Flow for Academic Chip Tapeout (Thursday, August 21, 2025)
• Ansys Announces Agreement to Offer Access to NVIDIA Omniverse Technology from within Simulation Solutions (Wednesday, August 20, 2025)
• Cadence Accelerates Development of Billion-Gate AI Designs with Innovative Power Analysis Technology Built on NVIDIA (Monday, August 18, 2025)
• Cadence Accelerates Development of Billion-Gate AI Designs with Innovative Power Analysis Technology Built on NVIDIA (Wednesday, August 13, 2025)
• Dnotitia Launches the World's First MCP-Based AI Agent Workstation with Integrated Vector Database (Tuesday, August 12, 2025)
• Rapidus adopts Teamcenter for Semiconductor Lifecycle Management (Thursday, July 31, 2025)
• Mike Yeager: 'Simulation Is Now Driving Product Design, Not Just Validating It' (Thursday, July 24, 2025)
• Axiomise Partners With Bluespec to Verify Its RISC-V Cores (Monday, July 21, 2025)
• How Mature-Technology ASICs Can Give You the Edge (Thursday, July 17, 2025)
• Thalia Design Automation launches AMALIA Platform 25.2 (Wednesday, July 16, 2025)
• Siemens collaborates with SK keyfoundry to launch 130nm automotive power semiconductor Calibre PERC PDK (Wednesday, July 16, 2025)
• IC'Alps Joins GlobalFoundries GlobalSolutions™ Ecosystem to Accelerate ASIC Development (Friday, July 11, 2025)
• IC'Alps Joins GlobalFoundries GlobalSolutions™ Ecosystem to Accelerate ASIC Development (Friday, July 11, 2025)
• Arteris Expands Multi-Die Network-on-Chip Design IP and Software (Wednesday, July 2, 2025)
• Wavetek Deploys Silvaco’s Victory TCAD™ to Drive Innovation in GaN-Based Connectivity Solutions (Tuesday, July 1, 2025)
• Synopsys Reinvents Semiconductor Design: AI-Driven EDA Tools Lead the Charge in Next-Gen Chip Innovation (Saturday, June 28, 2025)
• How Chip Startups Are Changing the Way Chips Are Designed (Wednesday, June 25, 2025)
• Siemens streamlines design and analysis of complex, heterogeneously integrated 3D ICs (Wednesday, June 25, 2025)
• Ausdia Solves Critical Design Flow Gap with OneSource Constraint Translation at DAC 2025 (Monday, June 23, 2025)
• Mirabilis Design Signs OEM Agreement with Cadence to Deliver VisualSim for System-Level Modeling and Performance Optimization (Monday, June 23, 2025)
• Siemens turbocharges semiconductor and PCB design portfolio with generative and agentic AI (Monday, June 23, 2025)
• From Rigid to Agile: Make the Shift from Open Source to Agnisys IDesignSpec (Friday, June 20, 2025)
• Keysight Enables AMD to Showcase Electrical PCI Express® Compliance up to 64 GT/s (Thursday, June 19, 2025)
• Siemens collaborates with Samsung Foundry on advanced node product certifications and EDA innovation (Wednesday, June 18, 2025)
• Cadence Accelerates SoC, 3D-IC and Chiplet Design for AI Data Centers, Automotive and Connectivity in Collaboration with Samsung Foundry (Tuesday, June 17, 2025)
• Synopsys Accelerates AI and Multi-Die Design Innovation on Advanced Samsung Foundry Processes (Tuesday, June 17, 2025)
• InCore Unveils SoC Generator Platform: From Idea to FPGA Validation in Minutes; Demonstrates Silicon Proof of Auto-Generated SoC (Monday, June 16, 2025)
• Imec achieves record-breaking RF GaN-on-Si transistor performance for high-efficiency 6G power amplifiers (Thursday, June 12, 2025)
• Cadence Advances Design and Engineering for Europe's Manufacturers on NVIDIA Industrial AI Cloud (Wednesday, June 11, 2025)
• OPENEDGES Collaborates with Renesas on Memory Subsystem IPs for Next-Generation MPU Platform Development (Wednesday, June 11, 2025)
• Siemens' PAVE360 to support new Arm Zena Compute Subsystems (Wednesday, June 11, 2025)
• Keysight and Synopsys Deliver an AI-Powered RF Design Migration Flow for Transition from TSMC's N6RF+ to N4P Process Node (Friday, June 6, 2025)