Andes AutoOpTune™ v1.0 accelerates software development by giving software developers the ability to automatically explore and choose the compiler optimizations to achieve their performance and code-size targets.
www.andestech.com, Jul. 10, 2025 –
Andes Technology, a leading provider of high-efficiency, low-power 32/64-bit RISC-V processor cores and a Founding Premier member of RISC-V International, today announced the release of Andes AutoOpTune™ v1.0 – an intelligent tool designed to automatically optimize and compile software objects by fine-tuning compiler options. Tailored to meet a wide range of software development demands, AutoOpTune™ streamlines and accelerates performance and code size tuning for software developers.
Andes AutoOpTune™ uses genetic algorithms to intelligently explore over 280 compiler options and identify the optimal settings based on the user’s goals, whether they are to maximize performance, minimize code size, or a balance of both objectives. The tool offers visual insights into the trade-offs of each configuration, empowering developers to make informed decisions without the need for time-consuming manual iterations. With its intuitive interface, AutoOpTune™ enables users to define optimization goals and constraints quickly, visualize result tradeoffs using distribution diagrams, and quickly select their preferred target or apply the best flags to a build configuration.
Benchmark results demonstrate significant improvements across all AndesCoreTM RISC-V processors running a range of applications: In code size reduction mode, embedded and audio workloads achieved up to 18% size reduction compared to GCC’s standard code size optimizations. With performance optimization mode, key SPECint2006 benchmarks achieved up to 37% better performance compared to GCC’s highest level of performance optimization. As the name implies, balanced mode makes more modest improvements on both code size and performance, with typical results in the range of 5%-10%. These improvements translate directly to faster load times, lower memory usage, improved performance, and power consumption, key advantages in resource-constrained environments.
Andes AutoOpTune™ is available as a separately licensable plugin of AndeSight™ v5.4 and supports all Andes RISC-V processors. Via simple option tuning and recompilation, developers can gain extra improvements on software projects in development and for silicon that has already been deployed.
“Andes AutoOpTune™ drastically reduces the time and effort needed for software optimization,” said Dr. Charlie Su, President and CTO of Andes Technology. “This release marks a significant milestone in helping developers maximize the performance and efficiency of Andes RISC-V cores.”
For more information, we welcome you to join us at the 2025 RISC-V Summit China, which will take place from July 16 to 19 at the Zhangjiang Science Hall in Shanghai. Andes Technology cordially invites you to visit us at Booth D25 on the 1st floor of the Zhangjiang Science Hall, where we will showcase our latest RISC-V innovations and applications.
About Andes Technology
As a Founding Premier member of RISC-V International and a leader in commercial CPU IP, Andes Technology (TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099) is driving the global adoption of RISC-V. Andes’ extensive RISC-V Processor IP portfolio spans from ultra-efficient 32-bit CPUs to high-performance 64-bit Out-of-Order multiprocessor coherent clusters. With advanced vector processing, DSP capabilities, the powerful Andes Automated Custom Extension (ACE) framework, end-to-end AI hardware/software stack, ISO 26262 certification with full compliance, and a robust software ecosystem, Andes unlocks the full potential of RISC-V, empowering customers to accelerate innovation across AI, automotive, communications, consumer electronics, data centers, and mobile devices. Over 16 billion Andes-powered SoCs are driving innovations globally. Discover more at www.andestech.com and connect with Andes on LinkedIn, X, Bilibili and YouTube.