Jul. 18, 2025 –
Cadence recently announced the tapeout of its LPDDR6/5X memory IP system solution, the industry’s first to support data rates of up to 14.4 Gbps.
This development coincides with JEDEC's official release of the JESD209-6 LPDDR6 standard. As such, the new solution is set to accommodate the rising computational and memory bandwidth demands of next-generation AI models.
Cadence’s LPDDR6/5X memory IP system integrates a fully-compliant PHY and controller architecture that operates at 14.4 Gbps, which is approximately 50% faster than previous LPDDR5X solutions. The PHY architecture is derived from Cadence’s earlier GDDR6 and LPDDR5X platforms but offers specific enhancements such as dynamic feedback equalization (DFE), feed-forward equalization (FFE), and continuous-time linear equalization (CTLE) to maintain signal integrity at high speeds. Cadence claims that per-bit read and write delay adjustments, along with fine-grain delay tuning, unlock powerful timing calibration across variable system conditions.
To support scalability and design flexibility, the IP system offers hardened PHY macros for multiple floorplans, bump map configurations, and soft RTL macros for the controller. Cadence claims that this modularity supports both monolithic SoC designs and chiplet-based architectures through Cadence’s UCIe-based framework. On the logic level, low-frequency, top-level clocks simplify timing closure in complex digital designs.
Low-power features are also a central element of the system’s design. For example, the controller supports multiple dynamic frequency scaling (DFS) modes and low-power states such as VDD idle and VDD light sleep. Integrated reliability features include parity checking, error correction code (ECC), and scrubbing support. Additionally, the solution comes with a comprehensive LPDDR6 memory model for verification, which provides protocol checks and functional coverage to speed integration into SoCs.