TSMC's exit from GaN production has sparked considerable speculation.
www.eetasia.com, Jul. 23, 2025 –
Following Navitas’ partnership announcement with PSMC to fulfill the latter’s Gallium Nitride (GaN) wafer requirements, the exit of Taiwan Semiconductor Manufacturing Company (TSMC) from GaN production has sparked considerable speculation.
Taipei Times’ reporting on TSMC’s termination of its GaN foundry services by 2027 mentioned a “shift in market dynamics” leading to the world’s largest contract semiconductor chip manufacturer’s exit.
The “shift in market” could refer to the dwindling profits thanks to the high manufacturing costs of using GaN, one of the well-recognized factors limiting its adoption despite the notable efficiency it brings to power electronics.
This concern persists even with the smooth transition to grow GaN on Si and SiC substrates, which aims to reduce manufacturing costs. While the latter might have been a determinative contributor, many more speculate that the rising competition from China is a strategic step.
Geopolitical risks
The Chinese government invested close to $47.5 billion in the next phase of the National Integrated Circuit Industry Investment Fund, often called the “Big Fund”. This investment, primarily aimed at expanding the manufacturing capacity of Chinese semiconductor players, sent ripples across the global supply chain.
Commercial Times, a Taiwanese business paper, reported a drop in the price of 6-inch SiC substrates to less than $500 per wafer due to a dramatic oversupply across mainland China, as many new fabs emerged in the region.
This is accompanied by a drop in demand for these wafers from the EV market, one of the factors leading to Wolfspeed’s bankruptcy. It also reported a related price drop of 8-inch wafers owing to a deflationary spiral in China, even though China isn’t at a mass production stage with 8-inch SiC substrates. The future profitability of GaN-on-SiC wafers remains volatile, as epitaxially growing GaN on SiC remains costly, despite customer expectations for prices to drop, which could trigger a deflationary spiral.
China’s pursuit of technological self-sufficiency and the subsequent investment in R&D is also bearing fruit now. Earlier this year, Chinese researchers from the JFS Laboratory research team in Wuhan announced the creation of an 8-inch N-polar GaN-on-Si wafer, which is reportedly capable of reducing production costs by 40%.
While this topology, along with a few other promising ones, hasn’t yet reached the mass production stage, its accessibility to Chinese manufacturers gives them a further upper hand in disrupting the global supply chain.
Furthermore, it is not as if Chinese manufacturers were the only rising competition in the GaN market. Although stagnation in the EV application of GaN persists, anticipation of its growth has still attracted substantial investments.
Apart from notable acquisitions, such as Infineon’s acquisition of GaN Systems and Power Integrations’ acquisition of Odyssey Semiconductor, and others in the past few years, a wave of strategic moves and investments by major global players has further intensified competition and innovation in the GaN market.
Japanese companies such as Sumitomo Chemicals and Sanken Electric are keen on advancing 6-inch GaN-on-GaN wafer technology with cost-effectiveness in mind.
In fact, Sanken Electric acquired Powdec just this June to enhance its expertise in GaN-on-GaN epitaxial wafer production. Other leading global players—including NXP, ROHM, Mitsubishi Electric, Qorvo, STMicroelectronics, Texas Instruments, and Efficient Power Conversion (EPC)—are also ramping up GaN R&D, product launches, and partnerships to capture opportunities, riling up the competition even more.
TSMC’s Advanced Packaging Focus
Considering the more overarching determinants of TSMC’s GaN exit, one cannot overlook their ambitious investment in their Arizona plant in the USA.
TSMC has now invested an additional $100 billion in the U.S. to expand into three new fabrication plants, two advanced packaging facilities, and a major R&D team center, aiming to fuel the AI boom with their semiconductors.
The semiconductor chip manufacturing company had already streamlined its investment priorities to cater to AI applications since 2020, when it first sought to invest in the Arizona plant. In this context, continued focus on GaN—despite its projected growth in EV and power electronics—would be increasingly peripheral to TSMC’s core roadmap.
Moreover, such a move is further complicated by geopolitical risks, as China currently controls around 98% of the global GaN supply. Against the backdrop of strained U.S.–China trade relations, relying on a China-dominated material introduces significant strategic and supply chain vulnerabilities.
As the chipmaker helps its GaN customers smoothly transition to other sources (Navitas has already signed with PSMC for the same), it has expressed plans to convert Hsinchu Fab 5, previously dedicated to GaN production, into a facility focused on advanced packaging technologies. Accompanied by significant domestic and international investments, it is expected to double TSMC’s advanced packaging capacity by 2026. However, the Taiwanese giant hasn’t revealed specific plans with these recent ventures.
TSMC may be exploring foundries for Chip-on-Wafer-on-Substrate (CoWoS) technology. This advanced packaging technology, developed by TSMC 3DFabric, is crucial for major tech companies seeking to boost the computing power of their chips, thereby enhancing their AI capabilities.
It involves placing multiple dies on a large silicon interposer, which acts as a high-density communication bridge between the chips. The packaging technology is what enables the most advanced AI chips to have a competitive bandwidth and low latency.
Furthermore, with CoWoS, there are upgrades to consider. Earlier this year, Nvidia’s CEO expressed the need to upgrade chip packaging with the Blackwell lineup. Nvidia primarily utilizes the CoWoS-S type of packaging for its chips, which uses a monolithic silicon interposer along with through-silicon vias (TSVs) to facilitate direct transmission of high-speed electrical signals between the die and the substrate.
Huang discussed Nvidia’s plans to transition to CoWoS-L (Chip-on-Wafer-on-Substrate with Local Silicon Interconnect) – a large package – with Blackwell, likely referring to mitigating yield issues with CoWoS-S.
Since chip design and packaging are too intertwined to neglect when trying to advance compute performance, it introduces a host of challenges for the packaging team, as packaging incurs most of the manufacturing cost and also creates bottlenecks. With this in mind, TSMC’s push for advanced packaging is inevitable.
TSMC is not keen on advancing with CoWoS, which optimizes die interconnects horizontally. Vertical stacking systems, which create a three-dimensional integrated circuit, further enhance bandwidth, speed, and energy efficiency in AI chips. Recent investments by TSMC may be specifically directed towards Wafer-on-Wafer (WoW) and Chip-on-Wafer (CoW) as part of the TSMC-SoIC platform.
On the other hand, the chipmaker might be looking to optimize its foundries for single-wafer processing to cater to changing market needs. As customer needs evolve to include complex chips with finer linewidths and more intricate 3D structures, economically commercializing this approach early may further strengthen TSMC’s foothold in the AI chip market.
Another plausible direction for these new facilities could be related to the recently announced System on Wafer-X (SoW-X) technology, which is capable of integrating at least 16 large computing and memory chips.
The company had expressed its plan to bring this technique to production by 2028, amidst its intense rivalry with Intel for AI chips in smartphones, automotive, and IoT applications.
TSMC will soon reveal its roadmap, but it is retreating to strengthen its already strong foothold in AI chips.
This article was originally published on EE Times.