Aug. 08, 2025, Aug. 08, 2025 –
The UCIe Consortium released the 3.0 version of its UCIe open standard, designed for high-speed, interoperable connectivity between chiplets in the same package.
The new version of the standard is fully backwards compatible with earlier versions, UCIe chair Debendra Das Sharma told EE Times.
“We want to make sure that things move in a backwards compatible manner so people’s investments are protected,” Das Sharma said. “We need to deliver the best power/performance/cost metrics that people can get, and then, of course, we have to continuously innovate… the key to making sure that the standard keeps getting deployed is to continuously innovate.”
Headline communication speeds for planar communication via UCIe-S (2D) and UCIe-A (2.5D) have been doubled to 48 and 64 GT/s, respectively.
“A lot of bandwidth-hungry applications, primarily in the AI space, but also in HPC and other areas, are shoreline-limited,” Das Sharma said. “Whatever shoreline you have is fixed by the die size, but we need to deliver more bandwidth, and the way to do that is to double the data rate.”
As a result of the changes, the bit error rate (BER) for the 64 GT/s mode was reduced from 10-15 to 10-12. Das Sharma said this isn’t a problem as external interconnects like PCIe and USB use 10-12, or 10-6 with forward error correction. This headroom needed to be used to increase the data rate.
At the request of DSP providers, support for continuous transmission protocols has been added to the new version of the specification. The goal is to enable uninterrupted data flow between SoC and DSP chiplets in wireless infrastructure, radio, and radar systems...