The new version of the UCIe standard has enhanced the data rate for chiplets to answer demand from bandwidth-hungry applications
www.eetasia.com, Aug. 19, 2025 –
The UCIe Consortium released the 3.0 version of its UCIe open standard, designed for high-speed, interoperable connectivity between chiplets in the same package.
The new version of the standard is fully backwards compatible with earlier versions, UCIe chair Debendra Das Sharma told EE Times.
“We want to make sure that things move in a backwards compatible manner so people’s investments are protected,” Das Sharma said. “We need to deliver the best power/performance/cost metrics that people can get, and then, of course, we have to continuously innovate… the key to making sure that the standard keeps getting deployed is to continuously innovate.”
Headline communication speeds for planar communication via UCIe-S (2D) and UCIe-A (2.5D) have been doubled to 48 and 64 GT/s, respectively.
“A lot of bandwidth-hungry applications, primarily in the AI space, but also in HPC and other areas, are shoreline-limited,” Das Sharma said. “Whatever shoreline you have is fixed by the die size, but we need to deliver more bandwidth, and the way to do that is to double the data rate.”
As a result of the changes, the bit error rate (BER) for the 64 GT/s mode was reduced from 10-15 to 10-12. Das Sharma said this isn’t a problem as external interconnects like PCIe and USB use 10-12, or 10-6 with forward error correction. This headroom needed to be used to increase the data rate.
At the request of DSP providers, support for continuous transmission protocols has been added to the new version of the specification. The goal is to enable uninterrupted data flow between SoC and DSP chiplets in wireless infrastructure, radio, and radar systems.
The issue had been a mismatch between ADC frequencies and link frequencies; this previously required two synchronised PLLs, which could introduce noise into noise-sensitive circuits. The new version of UCIe maps ADC and DAC transmission protocols onto the existing “raw mode,” allowing links to operate at the same data rate as data generation.
Enhanced runtime recalibration and L2 state (the deep power-saving state) help save power. Other features help with managing firmware download across multiple chiplets, new functions to prioritize transmission of low-latency messages over the sideband, and features to help in the event that an emergency throttle or shutdown is needed.
Das Sharma said that new features for the standard are prioritized based on a combination of how straightforward they are to implement and how useful they would be.
“Some things have a longer lead time, so of course, we are working on them, but some things may not be ready for prime time,” he said. “Even if a feature misses a major release, we’ll keep it in the bucket… That’s the nature of the beast – some are harder to tackle and some are easier from a time perspective.”
Ultimately, it is a democratic process, Das Sharma said.
“In the end, it depends on how much bandwidth people are willing to spend and how many review cycles are going to happen,” he said.
The standard isn’t tied to any particular release cadence, Das Sharma said; rather, release cadence reflects the demand from member companies.