Aug. 21, 2025 –
Morgan State University (MSU) recently received an Apple Innovation Grant, designed to support engineering schools as they develop their silicon and hardware technologies. The New Silicon Initiative (NSI) is designed to inspire and prepare students for careers in hardware engineering, computer architecture, and silicon chip design.
Innovative professors, such as MSU's Dr. Kevin Kornegay and others responsible for delivering on the NSI goals, are leveraging the funding and support to create invaluable, hands-on experiences for their students. MSU faculty can enhance the NSI curriculum by inviting subject matter experts to provide guest lectures on topics such as integrated circuit design and computer architecture, providing practical insight regarding the theory and practice of silicon design. The course sequence starts with "Introduction to Electrical and Computer Engineering" (EEGR 105), where sophomores learn hands-on skills in circuit design, and works up to the critical class in the NSI program: the new "Tapeout Course in Digital Integrated Circuit Design" (EEGR 463). EEGR 463 ran in parallel with a similar course offered at UC Berkeley, where the lectures, assignments, and labs were the same, and the UC Berkeley instructors were in lock step with the teaching assistants at MSU.
“In collaboration with UC Berkeley and industry partners Cadence, Intel, and others, students enrolled in my EEGR 463 course at MSU are getting invaluable hands-on experience designing chips from RTL to fabrication. By leveraging the Intel 16 and the Cadence tool flow, including Genus, Innovus, Tempus, and Pegasus technologies, students take their ideas from concept to reality, setting themselves apart from others looking to launch a career in the electronics industry.”
- Kevin Kornegay, Eugene DeLoatch Endowed Professor in IoT, Department of Electrical and Computer Engineering, Morgan State University
Tapeout is the final design process before a circuit is sent for manufacturing, so in this course, student teams create the design specification and implement the physical design and verification for tapeout. Students in Dr. Kornegay's course had a successful VLSI tapeout using the Intel PDK and leveraging the Cadence-based tool flow to create a chip from idea to implementation using Intel's 16nm FinFET technology chip fabrication facility. This success indicates the impact funding can have and how it will be instrumental in getting these students positions with leading companies in the industry.