Aug. 22, 2025 –
During the recent EE Times chiplets events in person in San Francisco and also the virtual event, it was clear that there’s a huge appetite to learn more about and understand the topic of chiplets. Conceptually it’s not new, but we are at a stage in chip design when complexity demands a more process-driven approach to designing with chiplets to reduce costs and development time, even though the use of multiple dies or chiplets creates new challenges.
As we saw at our events, there were many questions as well as examples of what’s already being deployed. One of the speakers at our event, Eddie Ramirez, VP of the infrastructure business at Arm, said after the event in a blog, “The chiplet era is underway. Walking through Moscone Center in San Francisco recently during the 62ndDAC, one thing jumped out at me: that reality was impossible to ignore – not just in the technology demonstrations, but in the conversations happening between foundries, IP vendors, OEMs and design houses. We’ve moved from asking “if” chiplets will scale to collaboratively solving “how” we design, validate and deploy multi-vendor systems across an integrated ecosystem.
In another recent announcement, Arteris said that AMD had licensed its FlexGen network-on-chip (NoC) interconnect IP for its next generation of AI chiplet design, providing high-performance data transport in AMD chiplets powering AI across the company’s broad portfolio.