According to Wccftech, citing sources, Rapidus is preparing its cutting-edge 2nm node, named "2HP," which is expected to deliver logic density on par with TSMC's N2 and, more notably, well ahead of Intel's 18A.
www.trendforce.com, Sept. 01, 2025 –
Rapidus 2HP is reported to reach a logic density of 237.31 MTr/mm², nearly matching TSMC's N2 at 236.17 MTr/mm², according to sources cited by the report. The report further highlights that both nodes adopt High Density (HD) cell libraries — with a 138-unit cell height on a G45 pitch — configurations designed to maximize logic density, suggesting comparable transistor counts.
As for Intel, its 18A node, despite being a smaller node size, is reported at 184.21 MTr/mm² — a comparatively lower density. The report, citing sources, explains that Intel’s use of BSPDN contributes to this outcome, as it occupies part of the front-side metal layers and reduces the density measured in the HD library. However, the report notes that Intel places greater emphasis on performance-per-watt rather than raw density, so higher logic density is not its primary goal, particularly as 18A is intended largely for internal use.
Rapidus 2nm PDK Set for Q1 2026, Mass Production Targeted for 2027
Rapidus will make its 2nm PDK available to customers in the first quarter of 2026, according to Wccftech. The Japanese company has been advancing quickly. According to TechPowerUp, Rapidus has successfully taped out a 2nm GAA test chip and is targeting high-volume production in 2027. The report adds that the chip was built with EUV tools from ASML and has already met all of its initial electrical requirements. Looking ahead to mass production in 2027, Rapidus’ CEO stated that the IIM-1 fab is expected to produce roughly 25,000 wafers per month, as cited by the report.
TechPowerUp also notes that by 2027, Rapidus is likely to be one or two nodes behind TSMC, and possibly even Intel. The report adds that to differentiate itself, the company is focusing on agility, highlighting a proprietary all-single-wafer process with a turnaround time of just 50 days, compared with about 120 days for the standard batch–single-wafer mix.