Design & Reuse

Global IP Core Announces the Availability of the NavIC LDPC/BCH Decoder FEC IP for Immediate Integration

Sept. 05, 2025 – 

Global IP Core Sales - The NAVIC LDPC/ BCH Decoder FEC is developed for satellite navigation applications.

Benefits

  • Low Area Design
  • Low-power and low-complexity design
  • Maximum likelihood decoder
  • Iterative Decoding
  • Irregular parity check matrix
  • Min-sum algorithm
  • Soft-decision decoding

Features

  • Compliant with ‘ISRO-NAVIC-ICD-SPS-L1-1.0’ standard [1]
  • Supports the BCH decoding for subframes (TOI) signal

Key Features

  • Throughput matching the required specifications
  • Bit-error-rate (BER) and block-error-rate (BLER) performance meet the required specifications
  • Supports the deinterleaver and LDPC decoder for subframes 2 and 3

Applications

  • Satellite Navigation
  • Global Positioning Service receiver

Please contact us for more information at info@global-ipc.com or check out our product portfolio at www.global-ipc.com

About Global IP Core Sales

Global IP Core Sales® was founded in 2021 and provides state-of-the-art IP Cores for the Semiconductor market. The majority of our products are silicon proven and can be seamlessly implemented into FPGA and ASIC technologies. Global IP Core Sales® will assist you with your IP Core and integration needs. Our mission is to grow your bottom line.