Sept. 11, 2025 –
Sydney, Australia — Perceptia Devices, a leader in low-jitter clocking IP, today announced the commencement of a port of its proven pPLL03 phase-locked loop (PLL) to Samsung Foundry’s 8LPU process node.
The pPLL03 is Perceptia’s ultra-low jitter, high-performance PLL IP core targeted at demanding SoC applications including AI accelerators, microprocessors, ADC/DAC sampling clocks, and high-speed digital subsystems. The port to Samsung’s 8LPU process forms part of Perceptia’s ongoing strategy to deliver robust, silicon-proven clocking solutions across leading-edge foundry technologies. Key features of pPLL03 include:
Samsung’s 8LPU process is based on FinFET technology and provides improved power and area efficiency over its 10nm predecessor. The pPLL03 port will take advantage of process-specific enhancements to ensure optimal analogue performance, low-noise operation, and ease integration with contemporary digital SoC design flows.
“Samsung’s 8LPU process offers an attractive combination of performance, density, and power efficiency for advanced SoC designs,” said Tim Robins, VP Engineering at Perceptia. “Bringing our pPLL03 IP to this node enables our customers to deploy mission-critical clocking in some of the most demanding environments, from 5G infrastructure to AI acceleration and advanced processors.”
Perceptia’s all digital PLL architecture is uniquely suited for FinFET technologies, replacing finicky analog circuits with DSP calculations. In addition, Perceptia’s development methodology includes rigorous analogue/mixedsignal simulation, comprehensive verification, and silicon characterisation. Ensuring the pPLL03 port to Samsung 8LPU will result in a production ready PLL.
Availability of the design kit for pPLL03 in Samsung 8LPU is targeted for Q1 2026. Early access and customisation engagements are available for qualified customers.
pPLL03 is a compact, low-jitter phase-locked loop (PLL) IP core optimised for advanced process nodes. Delivering output clock frequencies up to 5GHz, pPLL03 is designed for use in a wide range of high-performance applications including high-performance computing, AI acceleration and timing-critical logic, it delivers superior jitter and integration flexibility. pPLL03 is especially suited for designs with many clock domains. pPLL03 enables designers to confidently implement advanced timing architectures without compromising on area or power.
Perceptia Devices is an IP and design services provider, based in Sydney, Australia. With a focus on PLLs and precision timing, Perceptia supports customers across a wide range of applications including wireless communications, AI/ML, data converters, IoT, and mixed-signal SoCs with high performance, low area PLLs. For more information or to request the datasheet, please contact: