www.eetimes.com, Sept. 26, 2025 –
The design tool offerings of the top three EDA houses showcased at TSMC’s annual U.S. event once more affirm the two defining trends in the current semiconductor landscape: artificial intelligence (AI) and chiplets. TSMC’s Open Innovation Platform (OIP) Ecosystem Forum brings together partners to demonstrate their design advancements of TSMC’s latest process nodes and packaging technologies.
The EDA trio’s announcements at the event encompass new AI flows and multi-die innovations relating to 3D IC, advanced packaging, and chiplets. The advancements in AI and chiplet realms are intertwined, paving the way for high-performance AI and HPC chips that serve compute-intensive workloads.
The EDA trio—Cadence Design Systems, Siemens EDA, and Synopsys—is working closely with TSMC to facilitate AI-driven circuit and system designs, as well as accelerate multi-die innovations, making chiplets a commercial reality beyond large semiconductor outfits like AMD, Intel, and Nvidia.
These collaborative pacts with the Taiwanese fab also reveal the 2026 product roadmaps for AI- and chiplets-related technology initiatives. Moreover, they provide a greater visibility on how TSMC’s technologies for multi-die stacking and advanced packaging are evolving in the age of AI and chiplets.
AI inside EDA flows
Cadence displayed its AI-driven design solutions for optimal power, performance, and area (PPA) on TSMC’s N2 process node. TSMC has validated these AI-driven features—such as automated design rule check (DRC) violation fixing assistance—to enable faster design closure and greater efficiency in the development of AI chips manufactured on its N2 process node.
Cadence also demonstrated the Innovus+ AI assistant on its digital flows to showcase the AI-driven implementation. Innovus+ utilizes AI tools to integrate RTL synthesis and implementation technologies into a cohesive platform, delivering robust PPA results while simplifying complex design workflows.