Nov. 13, 2025, Nov. 13, 2025 –
By Pax Wang, Division Director of Technology Development, UMC
EETimes
The rapid migration of AI from the cloud to edge devices is fueling explosive growth in edge AI. Sectors like automotive, PCs, robotics, smartphones and surveillance are accelerating adoption, with the number of edge AI devices projected to grow at 17% CAGR to more than 2 billion units by 2030.
Compared to cloud AI systems, which deliver up to 10,000 TOPS of computing power and require massive power budgets and high dollar investments, IC design for edge AI applications is completely different. Edge AI devices typically only require 1-50 TOPS with strict power (0.01-1W) and cost ($10-$1,000) constraints. This forces chip designers to address bandwidth, performance, form factor, thermal and cost challenges simultaneously.
Traditional planar chip architectures are reaching their limits as multimodal AI applications demand more bandwidth and compute resources, increasing chip area and power consumption. To address these challenges, the industry is increasingly embracing 3D vertical stacking, integrating processors, memory and other modules within a single package atop interposers.
The vertical stack approach shortens interconnects, which reduces signal loss and latency, lowers power use and enables more compact devices. The modular design of vertical stacking also improves yield and cost control.