February 12, 2026 -
True innovation in the year to come boils down to the semiconductor industry's ability to solve the looming crisis around data movement.
By Michal Siwinski, Arteris
The priorities of the semiconductor industry have fundamentally shifted. In earlier generations of chip design, raw processing power reigned supreme, often exemplified by performance, power, and area (PPA) concerns. The availability of high bandwidth memory and processing in advanced nodes that stretch toward Angstroms, together with related advances in cache hierarchies, the expanding use of chiplets and multi-die chip scaling, have largely brought these capabilities in line with today’s cross-industry demands. Yet the overall performance can still be constrained by another often underappreciated pillar of computing. No matter how capable individual XPU clusters, memories, or logic blocks are, their advantages can be negated if the interconnected system cannot efficiently move data between them.
The interconnect network, also known as the network-on-chip (NoC), is at the heart of modern advanced semiconductors—with a dozen or more NoCs as part of each chiplet, and even more used in multi-die system-on-chip (SoC) devices, representing about 10% of the total silicon. These NoCs are responsible for ensuring that data is where it needs to be at the right time and within the physical constraints of the underlying silicon to ensure optimal performance.