February 23, 2026 -
The 32-bit RISC-V IP core- TAE520 is a production-proven, extracted from production chips, delivering performance competitive with R52 while offering superior area efficiency, higher maximum operating frequency, and improved code density, build DCLS functional security architecture, and support Split/Lock mode. It achieves up to 5.83 CoreMark/MHz and 2.81 DMIPS/MHz, built on a 6 stage pipeline that supports the RV32GCBP instruction set.
Automotive-grade processor compliant with ISO 26262, supporting ASIL-B to ASIL-D systems. Features Dual-Core Lockstep (Split/Lock modes), PPMA, Stack Monitor, N-Trace, cache coherency, and comprehensive hardware safety mechanisms including bus and SRAM protection with non-safety module isolation. Supports RTOS, μClinux, and Linux with SPMP.
Suitable for designs with high requirements for interrupt processing speed, such as industrial control, medical device control, storage device control, modem, 5G communication, streaming media transmission, etc., especially suitable for in-vehicle ECU/DCU and automotive-grade IC design fields.
The TAE520 complements T2M’s full range of RISC‑V IP cores portfolio covering more than 20 cores, which spans ultra‑low‑power MCU‑class designs to high‑performance embedded processors comparable to M0 - A55. With both 32‑bit and 64‑bit CPUs, optional accelerators, and safety‑ready cores (ASIL‑B/D), the portfolio empowers customers to develop differentiated silicon across automotive, industrial, consumer, medical, and edge‑AI markets.
Meet T2M at MWC, Barcelona and Embedded World, Nuremberg, Germany
Schedule an appointment with our team to explore how our RISC-V IP cores can enhance your embedded systems.
Please send meeting requests to contact@t-2-m.com.
About Us: T2M provides a broad portfolio of semiconductor IPs, including interface IPs (USB, PCIe, DDR, MIPI, HDMI), programmable SerDes, and Wireless IPs,: Cellular IPs (5G, NB-IoT), Satcom IPs (GNSS, SDR, NTN), BT/BLE (Controller and RF) IPs and Wi-Fi RF IPs available in major Fabs in process geometries along with ASIC services.