February 26, 2026 -
SEALSQCorp (NASDAQ: LAES) is strategically refocusing its quantum computing efforts on silicon-based architectures to leverage existing semiconductor technology, a move the company believes is crucial for long-term scalability. The Geneva-based developer of semiconductors, PKI, and post-quantum technology hardware and software is prioritizing silicon spin qubits and electrons-on-helium platforms, both of which can be fabricated and scaled using established CMOS processes. This emphasis on CMOS compatibility isn’t merely a manufacturing preference, but a system-level enabler for dense control arrays and high-speed signal routing necessary for quantum processors. “From our perspective, this technology alignment is a real advantage over other quantum approaches, such as superconducting or ion-trap systems,” said Carlos Moreira, Founder and CEO of SEALSQ, adding that silicon-based designs “are designed from the start to evolve within the semiconductor ecosystem.” Alongside hardware development, SEALSQ is also integrating post-quantum cryptography and hardware-based trust mechanisms to ensure secure quantum systems.
SEALSQ Focuses on CMOS-Compatible Quantum Architectures
SEALSQCorp is intensifying its focus on developing quantum computing architectures deeply compatible with complementary metal-oxide-semiconductor (CMOS) technology, a move signaling a commitment to long-term scalability within the rapidly evolving quantum landscape. The Geneva-based company, trading on NASDAQ as LAES, believes aligning quantum processors with established semiconductor manufacturing processes is crucial for practical advancement, specifically concentrating investments on silicon spin qubits and electrons-on-helium platforms. These approaches offer a pathway to fabrication, integration, and scaling using existing CMOS capabilities, a significant advantage over other quantum modalities. Both silicon spin qubits and electrons-on-helium architectures present promising avenues for CMOS compatibility; the former leverages electrons in silicon using chip-making methods akin to CMOS, while the latter employs electrons above superfluid helium on a silicon chip with CMOS-compatible controls.