March 23, 2026 -
New Synopsys tools target AI chip complexity as verification bottlenecks hit production schedules
Synopsys has introduced a new set of software and hardware-assisted design tools aimed at accelerating AI chip development, with direct implications for verification cycles, design costs, and time-to-tapeout. The announcement, made on 11 March, targets a growing constraint in semiconductor production: the verification bottleneck as AI workloads drive up design complexity.
According to Reuters, the company’s latest tools are designed to handle increasingly complex AI chip architectures, where traditional verification flows struggle to keep pace with design scale. Reuters reported that Synopsys is focusing on “software tools for designing advanced chips used in artificial intelligence applications,” highlighting rising demand from hyperscalers and chipmakers building custom silicon.
The updated toolchain integrates software-defined hardware-assisted verification, combining simulation and emulation to reduce turnaround times. In a statement carried by PR Newswire, the company said the approach “enables faster software bring-up and system validation,” targeting one of the most time-intensive phases of chip production.