April 7, 2026 -
TES Electronic Solutions GmbH offers an Integer-N Phase-Locked Loop (PLL) IP designed for high-frequency clock generation and frequency synthesis in on-chip applications. Built on X-FAB XT018-0.18µm BCD-on-SOI CMOS technology, this integrated PLL features an integrated loop filter, a high-performance VCO, and robust stability, making it ideal for applications demanding precise timing, low jitter, and long-term reliability. The IP is already silicon-proven and ready for mass production.
Key Features
Key Benefits
For more information on this and other IP solutions, visit the TES IP products page.
Contact
For inquiries, please email info@tes-dst.com
About TES
With over 20 years of experience in ASIC design and embedded graphics IP, TES is a one-stop partner for high-performance semiconductor solutions. Our IP portfolio includes highly customizable 2D, 2.5D, and 3D GPUs, display controllers, and a wide range of analog and digital IP blocks, ranging from SiGe RF to industrial ASIC solutions.
Headquartered near Stuttgart, Germany, TES Electronic Solutions GmbH serves a global customer base, with design operations in Stuttgart and graphics IP development in Hamburg. Learn more at www.tes-dst.com.