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System on Chip design resources
System on Chip design resources
August 3, 2026 -
The computing demands of AI are pushing chip design beyond what a single piece of silicon can efficiently deliver.
“You have this beast that needs to be fed,” said Raja Swaminathan, corporate vice president at AMD, speaking alongside other executives from Broadcom, TSMC, and Synopsys at the 2026 Synopsys Executive Forum, part of Synopsys Converge. “The AI compute curve demands more than 4× per year scaling. You need a lot of innovation beyond what Moore’s Law is giving us.”
That innovation is increasingly happening at the system level, with multi-die designs that integrate chiplets on ever-larger substrates. Industry roadmaps already point toward system-on-wafer and, eventually, system-on-panel architectures.
The consequences are multifold. Multi-die systems are pushing multiphysics upstream, blurring domain boundaries, and accelerating the adoption of AI tools and digital twins.
One consequence of multi-die design is that multiphysics analysis now must happen earlier in the process. Stacking and integrating multiple dies introduces new, often unexpected thermal, mechanical, and power effects.
“We should not be surprised by multiphysics issues at the very end of critical programs,” said Swaminathan. “Stress analysis, thermal analysis, IR, and power distribution analysis all need to be ‘shifted left’ into prototyping and construction.”
This represents a fundamental change in design logic.
“When we designed chips before, packaging and multiphysics were afterthoughts,” said Asad Khamisy, senior vice president of engineering at Broadcom. “Now things are reversed. Multiphysics comes first, and it drives your product definition.”
He pointed to the power density constraints in the top and bottom dies of a 3D stack as an example.
“You have to develop a thermal model for how you will cool the chip even before you decide on your architecture,” Khamisy said.
But moving analysis into architectural exploration creates a new challenge: balancing accuracy and turnaround time.
“It’s a tradeoff,” said Shankar Krishnamoorthy, chief product development officer at Synopsys. “Do you really need the temperature gradient down to the last 0.5 degree Celsius, or can it be a one- or two-degree resolution? And do you want that answer in 10 minutes, or do you want the answer in 12 hours?”
A staged modeling strategy, he added, can provide a middle ground — using fast, approximate models to narrow the design space early, then increasing fidelity as the architecture converges.