Catalog of SIP Cores
System on Chip design resources
System on Chip design resources
November 9, 2026 -
Eight years ago, GlobalFoundries announced that it would stop the R&D of 7nm FinFET process. Eight years later, this wafer foundry is trying to re-enter the competition of advanced logic processes through another technical route.
In an interview with Tom's Hardware, Sudipto Bose, Vice President of GlobalFoundries' FD-SOI business unit, elaborated on the company's new-generation FDX Fusion process. Based on FD-SOI (Fully Depleted Silicon-On-Insulator), this technology adopts advanced planar transistors without EUV lithography, aiming to achieve 7nm-level power consumption and performance while reaching 8nm-level logic density.