Options ‘slice across tech barriers’
Rick Merritt, EETimes
9/22/2016 09:15 PM EDT
SAN JOSE, Calif. – Taiwan’s largest semiconductor kitchen released its latest menu, a 3D matrix that spans process, packaging and applications-specific options.
TSMC described at an event here FinFET processes down to 7nm it will serve up over the next few months as well as an expanding set of 3D packaging options. “We are getting into a 3D x 3D era that will carry us into the next decade, said Jack Sun, chief technologist and vice president of R&D at TSMC.
The foundry will have volume production of its 10nm process before the end of the year and be ready to take orders for its 7nm process by April, said Sun. He showed two new variants in the works for the so-called InFO stacks analysts say Apple is now using for its A10 Fusion SoC. And he sketched out a handful of other 3D packaging options for different uses.
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