Bluespec Returns from Landmark RISC-V Summit; CTO Nikhil Leads Discussion on ISA Formal Spec
FRAMINGHAM, Mass.-- January 28, 2019 -- Bluespec has just returned from the first-ever RISC-V Summit in Santa Clara, CA. Packed with over 1,100 attendees from more than 20 countries around the world, the attendance alone signals a seismic shift in RISC-V interest and global importance.
With extraordinary keynote presentations from Facebook, SiFive, and Western Digital, the summit was filled with thought leaders in the RISC-V community. Attending for Bluspec was CTO Rishiyur Nikhil, who was proud to serve as the formal chair for the summit’s lively technical session on ISA Formal Spec on Thursday, December 6th.
In a spirited “state of the union” on the topic, Nikhil explained the colossal shift of instruction set language from English to math, which has enabled a far more precise means of communicating RISC-V instructions. This, Nikhil informed the crowd, marks yet another massive change brought on by RISC-V, as it sweeps across the world, redefining how we build our future.
Other highlights included a captivating technical talk by Symbiotic EDA’s Clifford Wolf, a surprise announcement from Western Digital’s Martin Fink, and an insightful presentation on security from RISC-V Foundation Vice-Chair, David Patterson. Patterson's talk emphasized the revolutionary power of RISC-V as it ushers security development out of a closed, corporate system and into the open, where many more eyes (and minds) can look at it. There is no doubt that RISC-V will play a critical role in the future of security.
2019 is already filled with workshops and conferences around the globe that will continue to push RISC-V into the forefront of CPU technology. Bluespec is excited to be involved with a number of these events and looks forward to playing a major role in the RISC-V movement in the year to come.
|
Related News
- Think Silicon demonstrates early preview of Industry's first RISC-V ISA based 3D GPU at the RISC-V Summit
- Ventana CEO to Deliver a Keynote at RISC-V Summit Europe
- Andes Technology Showcases Leadership in AI and Automotive Applications at RISC-V Summit Europe 2024
- MerlinTPS Partners with Bluespec to Provide Urgently Needed GPS Augmentation and Backup Without Satellites
- Frontgrade Gaisler Leads the Way in RISC-V Processor Development for Space Applications
Breaking News
- Arteris Joins Intel Foundry Accelerator Ecosystem Alliance Program to Support Advanced Semiconductor Designs
- SkyeChip Joins Intel Foundry Accelerator IP Alliance
- Siemens and Intel Foundry advance their collaboration to enable cutting-edge integrated circuits and advanced packaging solutions for 2D and 3D IC
- Cadence Expands Design IP Portfolio Optimized for Intel 18A and Intel 18A-P Technologies, Advancing AI, HPC and Mobility Applications
- Synopsys and Intel Foundry Propel Angstrom-Scale Chip Designs on Intel 18A and Intel 18A-P Technologies
Most Popular
- QuickLogic Delivers eFPGA Hard IP for Intel 18A Based Test Chip
- Siemens collaborates with TSMC to drive further innovation in semiconductor design and integration
- Aion Silicon Joins Intel Foundry Accelerator Design Services Alliance to Deliver Next-Generation Custom SoCs at Scale
- TSMC Unveils Next-Generation A14 Process at North America Technology Symposium
- BOS Semiconductors to Partner with Intel to Accelerate Automotive AI Innovation
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |