NVM OTP in UMC (180nm, 153nm, 110nm, 90nm, 80nm, 55nm, 40nm, 28nm, 22nm)
Bluespec Returns from Landmark RISC-V Summit; CTO Nikhil Leads Discussion on ISA Formal Spec
FRAMINGHAM, Mass.-- January 28, 2019 -- Bluespec has just returned from the first-ever RISC-V Summit in Santa Clara, CA. Packed with over 1,100 attendees from more than 20 countries around the world, the attendance alone signals a seismic shift in RISC-V interest and global importance.
With extraordinary keynote presentations from Facebook, SiFive, and Western Digital, the summit was filled with thought leaders in the RISC-V community. Attending for Bluspec was CTO Rishiyur Nikhil, who was proud to serve as the formal chair for the summit’s lively technical session on ISA Formal Spec on Thursday, December 6th.
In a spirited “state of the union” on the topic, Nikhil explained the colossal shift of instruction set language from English to math, which has enabled a far more precise means of communicating RISC-V instructions. This, Nikhil informed the crowd, marks yet another massive change brought on by RISC-V, as it sweeps across the world, redefining how we build our future.
Other highlights included a captivating technical talk by Symbiotic EDA’s Clifford Wolf, a surprise announcement from Western Digital’s Martin Fink, and an insightful presentation on security from RISC-V Foundation Vice-Chair, David Patterson. Patterson's talk emphasized the revolutionary power of RISC-V as it ushers security development out of a closed, corporate system and into the open, where many more eyes (and minds) can look at it. There is no doubt that RISC-V will play a critical role in the future of security.
2019 is already filled with workshops and conferences around the globe that will continue to push RISC-V into the forefront of CPU technology. Bluespec is excited to be involved with a number of these events and looks forward to playing a major role in the RISC-V movement in the year to come.
|
Related News
- Think Silicon demonstrates early preview of Industry's first RISC-V ISA based 3D GPU at the RISC-V Summit
- Andes Technology to Exhibit Groundbreaking RISC-V Solutions for AI and Automotive at RISC-V Summit North America 2023
- Axiomise Heads to Silicon Valley Next Week for RISC-V Summit North America
- Bluespec's Accelerate-HLS Leverages RISC-V to Simplify and Speed the Development of HLS Applications
- Bluespec Launches New MCUX RISC-V Processor That Enables Developers to Implement Custom Instructions and Add Accelerators
Breaking News
- Synopsys Showcases EDA Performance and Next-Gen Capabilities with NVIDIA Accelerated Computing, Generative AI and Omniverse
- Spectral Releases Advanced Quality Assurance & Data Analytics tool to validate advanced node Memory Compilers
- TSMC and Synopsys Bring Breakthrough NVIDIA Computational Lithography Platform to Production
- After TSMC fab in Japan, advanced packaging facility is next
- A System On Module (SoM) developed by Electra IC: BitFlex-SPB-A7 FPGA SoM
Most Popular
- After TSMC fab in Japan, advanced packaging facility is next
- HBM3 Initially Exclusively Supplied by SK Hynix, Samsung Rallies Fast After AMD Validation, Says TrendForce
- Alphawave Semi Demonstrates 3nm Silicon-Proven 24Gbps Universal Chiplet Express (UCIe) Subsystem for High-Performance AI Infrastructure
- Weebit Nano to demo its ReRAM technology on GlobalFoundries' 22FDX® platform
- We'll Need Many More Fabs to Meet $1 Trillion by 2030 Goal
E-mail This Article | Printer-Friendly Page |