PLDA Announces Major PCIe 5.0 Design Win on Cutting Edge 5nm Process Node

August 1, 2019 -- PLDA, the industry leader in PCI Express® IP and interconnect solutions, today announced a major PCIe 5.0 design win on cutting edge 5nm process node. PLDA’s PCIe 5.0 Controller IP was selected not only for its solid design and unmatched compatibility with popular PCIe PHYs, but also for PLDA’s best-in-class tech support, its ease of customization and PLDA’s integration expertise.

PCIe 5.0 technology is experiencing a rapid adoption rate, fueled by the growing demand for more bandwidth in datacenters. PLDA’s silicon-proven PCIe IP provides a risk-free interface solution, giving customers peace of mind and a significant time-to-market advantage. In addition, PLDA and its team of expert architects and engineers go the extra mile to understand customer use cases and requirements and help with architecture choices, proposing design optimizations and assisting with critical implementation details.

PLDA was chosen versus the competition because they delivered an unmatched set of advantages including:

Pre-verified, pre-validated silicon IP
Assistance with IP integration
Highly-configurable IP, easily modified to meet exact design requirements via an intuitive GUI
A team of skilled engineers, ready to further tailor the IP to specific requirements and to provide design expertise beyond IP customization
Extensive PHY integration expertise and a large choice of pre-integrated, pre-validated PHY IP from multiple vendors and on a broad range of process nodes
A team of verification experts
Guidance and support from the RTL Sign-Off stage, to Tape-Out, and beyond

About PLDA PCIe 5.0 IP: PLDA’s PCIe 5.0 controller IP is available with either a native PCIe interface or with an AMBA AXI interconnect. Features of the IP include:

Configurable and scalable PCIe controller Soft IP designed for ASIC and FPGA implementation
Designed to the PCI Express 5.0, 4.0, and 3.1/3.0 specifications, as well as with version 5.x of the PHY Interface for PCI Express (PIPE) specification
Configurable to support endpoint, root port, switch port, and dual-mode topologies, allowing for a variety of use models

According to Arnaud Schleich, CEO of PLDA “We are proud to be working with leading edge customers who are deploying the latest PCIe technology in their SoCs on the most advanced nodes available today.” Schleich added, “Our long history of first time silicon success is an important advantage to early adopters of new technologies.”

More information:

You can access more information on PLDA’s PCIe 5.0 IP as follows:

Visit PLDA’s PCIe 5.0 IP product page at https://www.plda.com/products/xpressrich5 and https://www.plda.com/products/xpressrich5-axi
Visit PLDA’s exhibit at the Flash Memory Summit, August 6-8, 2019 at the Santa Clara Convention Center in booth #826. To register for the Flash Memory Summit, please visit https://flashmemorysummit.com

PLDA, the industry leader in PCI Express® IP and interconnect solutions, today announced a major PCIe 5.0 design win on cutting edge 5nm process node. PLDA’s PCIe 5.0 Controller IP was selected not only for its solid design and unmatched compatibility with popular PCIe PHYs, but also for PLDA’s best-in-class tech support, its ease of customization and PLDA’s integration expertise.

PLDA was chosen versus the competition because they delivered an unmatched set of advantages including:

Pre-verified, pre-validated silicon IP
Assistance with IP integration
Highly-configurable IP, easily modified to meet exact design requirements via an intuitive GUI
A team of skilled engineers, ready to further tailor the IP to specific requirements and to provide design expertise beyond IP customization
Extensive PHY integration expertise and a large choice of pre-integrated, pre-validated PHY IP from multiple vendors and on a broad range of process nodes
A team of verification experts
Guidance and support from the RTL Sign-Off stage, to Tape-Out, and beyond

About PLDA PCIe 5.0 IP: PLDA’s PCIe 5.0 controller IP is available with either a native PCIe interface or with an AMBA AXI interconnect. Features of the IP include:

Configurable and scalable PCIe controller Soft IP designed for ASIC and FPGA implementation
Designed to the PCI Express 5.0, 4.0, and 3.1/3.0 specifications, as well as with version 5.x of the PHY Interface for PCI Express (PIPE) specification
Configurable to support endpoint, root port, switch port, and dual-mode topologies, allowing for a variety of use models

More information:

You can access more information on PLDA’s PCIe 5.0 IP as follows:

Visit PLDA’s PCIe 5.0 IP product page at https://www.plda.com/products/xpressrich5 and https://www.plda.com/products/xpressrich5-axi
Visit PLDA’s exhibit at the Flash Memory Summit, August 6-8, 2019 at the Santa Clara Convention Center in booth #826. To register for the Flash Memory Summit, please visit https://flashmemorysummit.com